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ADF4117BRUZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
ADF4116/ADF4117/ADF4118
Rev. D | Page 16 of 28
CURRENT SETTINGSLDP
250µA
0
1
A5
X
X
•
•
X
X
A4
X
X
•
•
X
X
A3
0
0
•
•
1
1
A2
0
0
•
•
1
1
A1
0
1
•
•
0
1
A COUNTER
DIVIDE RATIO
0
1
•
•
6
7
B13
0
0
0
0
•
•
•
1
1
1
1
B12
0
0
0
0
•
•
•
1
1
1
1
B11
0
0
0
0
•
•
•
1
1
1
1
B3 B2 B1 B COUNTER DIVIDE RATIO
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
0
0
0
1
•
•
•
1
1
1
1
0
1
1
0
•
•
•
0
0
1
1
1
0
1
0
•
•
•
0
1
0
1
NOT ALLOWED
NOT ALLOWED
3
4
•
•
•
8188
8189
8190
8191
ADF4116
A5
0
0
0
•
•
1
1
1
A4
0
0
0
•
•
1
1
1
A3
0
0
0
•
•
1
1
1
A2
0
0
1
•
•
0
1
1
A1
0
1
0
•
•
1
0
1
A COUNTER
DIVIDE RATIO
0
1
2
•
•
29
30
31
ADF4117/ADF4118
1mA
N = BP + A, P IS PRESCALER VALUE. B MUST BE GREATER
THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT
VALUES OF N
X
F
REF
, N
MIN
IS (P
2
– P).
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0DB10
G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B3 B2 B1 A5 A4 A3 A2 A1 C2 (0) C1 (1)B4
CONTROL
BITS
13-BIT B COUNTER 5-BIT A COUNTER
CP GAIN
00392-032
Figure 32. A Counter/B Counter Latch Map
ADF4116/ADF4117/ADF4118
Rev. D | Page 17 of 28
M3
0
0
0
0
1
1
1
1
M2
0
0
1
1
0
0
1
1
M1
0
1
0
1
0
1
0
1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
AV
DD
R DIVIDER OUTPUT
ANALOG LOCK DETECT
(N CHANNEL OPEN DRAIN)
SERIAL DATA OUTPUT
(INVERSE POLARITY OF
SERIAL DATA INPUT)
DGND
TC4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TC3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TC2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TC1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TIMEOUT
(PFD CYCLES)
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
F1
0
1
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
F2
0
1
NEGATIVE
POSITIVE
F3
0
1
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
0
1
1
1
CE PIN PD2 PD1 MODE
X
X
0
1
X
0
1
1
F6
X
0
1
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
F4
0
1
1
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0DB10
TC4 TC3 TC2 TC1 F6 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)
CONTROL
BITS
MUXOUT
CONTROL
POWER-
DOWN 2
POWER-
DOWN 1
FASTLOCK
ENABLE
CP
THREE-
STATE
FASTLOCK
MODE
TIMER COUNTER
CONTROL
RESERVED
RESERVED
PD2X
DB20
X
RESERVED
XXX
PHASE
DETECTOR
POLARITY
PHASE DETECTOR
POLARITY
00392-033
COUNTER
RESET
Figure 33. Function Latch Map
ADF4116/ADF4117/ADF4118
Rev. D | Page 18 of 28
M3
0
0
0
0
1
1
1
1
M2
0
0
1
1
0
0
1
1
M1
0
1
0
1
0
1
0
1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
AV
DD
R DIVIDER OUTPUT
ANALOG LOCK DETECT
(N CHANNEL OPEN DRAIN)
SERIAL DATA OUTPUT
(INVERSE POLARITY OF
SERIAL DATA INPUT)
DGND
TC4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TC3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TC2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TC1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TIMEOUT
(PFD CYCLES)
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
F1
0
1
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
F2
0
1
NEGATIVE
POSITIVE
F3
0
1
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
0
1
1
1
CE PIN PD2 PD1 MODE
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
X
X
0
1
X
0
1
1
F6
X
0
1
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
F4
0
1
1
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0DB10
PD2 TC4 TC3 TC2 TC1 F6 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1)
CONTROL
BITS
MUXOUT
CONTROL
POWER-
DOWN 2
POWER-
DOWN 1
FASTLOCK
ENABLE
CP
THREE-
STATE
FASTLOCK
MODE
TIMER COUNTER
CONTROL
RESERVED
RESERVED
X
X
RESERVED
XXX
PHASE
DETECTOR
POLARITY
PHASE DETECTOR
POLARITY
00392-034
COUNTER
RESET
Figure 34. Initialization Latch Map
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

ADF4117BRUZ-RL

Mfr. #:
Buy ADF4117BRUZ-RL
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL SGL Integer-N 1.2 GHz
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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