X1227V8I-2.7 Datasheet X1227S8, X1227S8-2.7, X1227S8-2.7A | P10-P12

FN8099.2

May 8, 2006

POWER CONTROL OPERATION

The power control circuit accepts a V

and a V

BACK

input. The power control circuit powers the device from

BACK

when V

< V

BACK

- 0.2V. It will switch back to

power the device from V

when V

exceeds V

BACK

Figure 3. Power Control

REAL TIME CLOCK OPERATION

The Real Time Clock (RTC) uses an external

32.768kHz quartz crystal to maintain an accurate inter-

nal representation of the second, minute, hour, day,

date, month, and year. The RTC has leap-year correc-

tion. The clock also corrects for months having fewer

than 31 days and has a bit that controls 24 hour or

AM/PM format. When the X1227 powers up after the

loss of both V

and V

BACK

, the clock will not operate

until at least one byte is written to the clock register.

Reading the Real Time Clock

The RTC is read by initiating a Read command and

specifying the address corresponding to the register of

the Real Time Clock. The RTC Registers can then be

read in a Sequential Read Mode. Since the clock runs

continuously and a read takes a finite amount of time,

there is the possibility that the clock could change during

the course of a read operation. In this device, the time is

latched by the read command (falling edge of the clock

on the ACK bit prior to RTC data output) into a separate

latch to avoid time changes during the read operation.

The clock continues to run. Alarms occurring during a

read are unaffected by the read operation.

Writing to the Real Time Clock

The time and date may be set by writing to the RTC

registers. To avoid changing the current time by an

uncompleted write operation, the current time value is

loaded into a separate buffer at the falling edge of the

clock on the ACK bit before the RTC data input bytes,

the clock continues to run. The new serial input data

replaces the values in the buffer. This new RTC value

is loaded back into the RTC Register by a stop bit at

the end of a valid write sequence. An invalid write

operation aborts the time update procedure and the

contents of the buffer are discarded. After a valid write

operation the RTC will reflect the newly loaded data

beginning with the next “one second” clock cycle after

the stop bit is written. The RTC continues to update

the time while an RTC register write is in progress and

the RTC continues to run during any nonvolatile write

sequences. A single byte may be written to the RTC

without affecting the other bytes.

Accuracy of the Real Time Clock

The accuracy of the Real Time Clock depends on the

frequency of the quartz crystal that is used as the time

base for the RTC. Since the resonant frequency of a

crystal is temperature dependent, the RTC perfor-

mance will also be dependent upon temperature. The

frequency deviation of the crystal is a fuction of the

turnover temperature of the crystal from the crystal’s

nominal frequency. For example, a >20ppm frequency

deviation translates into an accuracy of >1 minute per

month. These parameters are available from the

crystal manufacturer. Intersil’s RTC family provides

on-chip crystal compensation networks to adjust load-

capacitance to tune oscillator frequency from +116

ppm to -37 ppm when using a 12.5 pF load crystal. For

more detail information see the Application section.

CLOCK/CONTROL REGISTERS (CCR)

The Control/Clock Registers are located in an area

separate from the EEPROM array and are only

accessible following a slave byte of “1101111x” and

reads or writes to addresses [0000h:003Fh]. The

clock/control memory map has memory addresses

from 0000h to 003Fh. The defined addresses are

described in the Table 1. Writing to and reading from

the undefined addresses are not recommended.

CCR access

The contents of the CCR can be modified by perform-

ing a byte or a page write operation directly to any

address in the CCR. Prior to writing to the CCR

(except the status register), however, the WEL and

RWEL bits must be set using a two step process (See

section “Writing to the Clock/Control Registers.”)

The CCR is divided into 5 sections. These are:

1. Alarm 0 (8 bytes; non-volatile)

2. Alarm 1 (8 bytes; non-volatile)

3. Control (4 bytes; non-volatile)

4. Real Time Clock (8 bytes; volatile)

5. Status (1 byte; volatile)

Each register is read and written through buffers. The

non-volatile portion (or the counter portion of the RTC)

is updated only if RWEL is set and only after a valid

write operation and stop bit. A sequential read or page

write operation provides access to the contents of only

one section of the CCR per operation. Access to

another section requires a new operation. Continued

BACK

Voltage

Off

X1227

FN8099.2

May 8, 2006

reads or writes, once reaching the end of a section, will

wrap around to the start of the section. A read or write

can begin at any address in the CCR.

It is not necessary to set the RWEL bit prior to writing

the status register. Section 5 supports a single byte

read or write only. Continued reads or writes from this

section terminates the operation.

The state of the CCR can be read by performing a ran-

dom read at any address in the CCR at any time. This

returns the contents of that register location. Additional

registers are read by performing a sequential read.

The read instruction latches all Clock registers into a

buffer, so an update of the clock does not change the

time being read. A sequential read of the CCR will not

result in the output of data from the memory array. At

the end of a read, the master supplies a stop condition

to end the operation and free the bus. After a read of

the CCR, the address remains at the previous address

+1 so the user can execute a current address read of

the CCR and continue reading the next Register.

ALARM REGISTERS

There are two alarm registers whose contents mimic the

contents of the RTC register, but add enable bits and

exclude the 24 hour time selection bit. The enable bits

specify which registers to use in the comparison between

the Alarm and Real Time Registers. For example:

– Setting the Enable Month bit (EMOn*) bit in combi-

nation with other enable bits and a specific alarm

time, the user can establish an alarm that triggers at

the same time once a year.

– *n = 0 for Alarm 0: N = 1 for Alarm 1

Table 1. Clock/Control Memory Map

Addr. Type

Reg

Name

Bit

Range

Default

76 5 4 3 2 10 (optional)

003F Status SR BAT AL1 AL0 0 0 RWEL WEL RTCF 01h

0037 RTC (SRAM) Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 19/20 20h

0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h

0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h

0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 00h

0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h

0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h

0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h

0013 Control

(EEPROM)

DTR 0 0 0 0 0 DTR2 DTR1 DTR0 00h

0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h

0011 INT Unused

0010 BL BP2 BP1 BP0 WD1 WD0 0 0 0 18h

000F Alarm1

(EEPROM)

Y2K1 0 0 A1Y2K21 A1Y2K20 A1Y2K13 0 0 A1Y2K10 19/20 20h

000E DWA1 EDW1 0 0 0 0 DY2 DY1 DY0 0-6 00h

000D YRA1 Unused - Default = RTC Year value (No EEPROM) - Future expansion

000C MOA1 EMO1 0 0 A1G20 A1G13 A1G12 A1G11 A1G10 1-12 00h

000B DTA1 EDT1 0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 00h

000A HRA1 EHR1 0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 00h

0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h

0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h

0007 Alarm0

(EEPROM)

Y2K0 0 0 A0Y2K21 A0Y2K20 A0Y2K13 0 0 A0Y2K10 19/20 20h

0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0005 YRA0 Unused - Default = RTC Year value (No EEPROM) - Future expansion

0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h

0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h

0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h

0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h

0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h

X1227

FN8099.2

May 8, 2006

When there is a match, an alarm flag is set. The occur-

rence of an alarm can be determined by polling the

AL0 and AL1 bits or by enabling the IRQ

output, using

it as hardware flag.

The alarm enable bits are located in the MSB of the

particular register. When all enable bits are set to ‘0’,

there are no alarms.

– The user can set the X1227 to alarm every Wednes-

day at 8:00 AM by setting the EDWn*, the EHRn*

and EMNn* enable bits to ‘1’ and setting the DWAn*,

HRAn* and MNAn* Alarm registers to 8:00 AM

Wednesday.

– A daily alarm for 9:30PM results when the EHRn*

and EMNn* enable bits are set to ‘1’ and the HRAn*

and MNAn* registers are set to 9:30 PM.

*n = 0 for Alarm 0: N = 1 for Alarm 1

REAL TIME CLOCK REGISTERS

Clock/Calendar Registers (SC, MN, HR, DT, MO, YR)

These registers depict BCD representations of the

time. As such, SC (Seconds) and MN (Minutes) range

from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM

indicator (H21 bit) or 0 to 23 (with MIL = 1), DT (Date)

is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.

Date of the Week Register (DW)

This register provides a Day of the Week status and

uses three bits DY2 to DY0 to represent the seven

days of the week. The counter advances in the cycle

0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical

value to a specific day of the week is arbitrary and may

be decided by the system software designer. The

default value is defined as ‘0’.

24 Hour Time

If the MIL bit of the HR register is 1, the RTC uses a

24-hour format. If the MIL bit is 0, the RTC uses a 12-

hour format and H21 bit functions as an AM/PM indi-

cator with a ‘1’ representing PM. The clock defaults to

standard time with H21 = 0.

Leap Years

Leap years add the day February 29 and are defined

as those years that are divisible by 4. Years divisible

by 100 are not leap years, unless they are also divisi-

ble by 400. This means that the year 2000 is a leap

year, the year 2100 is not. The X1227 does not correct

for the leap year in the year 2100.

STATUS REGISTER (SR)

The Status Register is located in the CCR Memory

Map at address 003Fh. This is a volatile register only

and is used to control the WEL and RWEL write

enable latches, read two power status and two alarm

bits. This register is separate from both the array and

the Clock/Control Registers (CCR).

Table 2. Status Register (SR)

BAT: Battery Supply—Volatile

This bit set to “1” indicates that the device is operating

from V

BACK

, not V

. It is a read-only bit and is set/reset

by hardware (X1227 internally). Once the device begins

operating from V

, the device sets this bit to “0”.

AL1, AL0: Alarm bits—Volatile

These bits announce if either alarm 0 or alarm 1 match

the real time clock. If there is a match, the respective

bit is set to ‘1’. The falling edge of the last data bit in a

SR Read operation resets the flags. Note: Only the AL

bits that are set when an SR read starts will be reset.

An alarm bit that is set by an alarm occurring during an

SR read operation will remain set after the read opera-

tion is complete.

RWEL: Register Write Enable Latch—Volatile

This bit is a volatile latch that powers up in the LOW

(disabled) state. The RWEL bit must be set to “1” prior

to any writes to the Clock/Control Registers. Writes to

RWEL bit do not cause a nonvolatile write cycle, so the

device is ready for the next operation immediately after

the stop condition. A write to the CCR requires both the

RWEL and WEL bits to be set in a specific sequence.

WEL: Write Enable Latch—Volatile

The WEL bit controls the access to the CCR and mem-

ory array during a write operation. This bit is a volatile

latch that powers up in the LOW (disabled) state. While

the WEL bit is LOW, writes to the CCR or any array

address will be ignored (no acknowledge will be issued

after the Data Byte). The WEL bit is set by writing a “1”

to the WEL bit and zeroes to the other bits of the Status

to 0 (by writing a “0” to the WEL bit and zeroes to the

other bits of the Status Register) or until the part powers

up again. Writes to WEL bit do not cause a nonvolatile

write cycle, so the device is ready for the next operation

immediately after the stop condition.

RTCF: Real Time Clock Fail Bit—Volatile

This bit is set to a “1” after a total power failure. This is

a read only bit that is set by hardware (X1227 inter-

nally) when the device powers up after having lost all

power to the device (both V

and V

BACK

go to 0V).

Addr 7 6 5 4 3 2 1 0

003Fh BAT AL1 AL0 0 0 RWEL WEL RTCF

Default 0 0 0 0 0 0 0 1

X1227

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

X1227V8I-2.7

Mfr. #:

Buy X1227V8I-2.7

Manufacturer:

Renesas / Intersil

Description:

IC RTC CLK/CALENDAR I2C 8-TSSOP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

X1227V8I-2.7

X1227V8I-2.7

Products related to this Datasheet