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X1227V8I-2.7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
25
FN8099.2
May 8, 2006
use the diode to charge a battery (especially lithium
batteries!).
Figure 20. Supercapacitor charging circuit
Since the battery switchover occurs at Vcc=Vback-
0.1V (see Figure 20), the battery voltage must always
be lower than the Vcc voltage during normal operation
or the battery will be drained. A second consideration
is the trip point setting for the system RESET- func-
tion, known as Vtrip. Vtrip is set at the factory at levels
for systems with either Vcc = 5V or 3.3V operation,
with the following standard options:
V
TRIP
= 4.63V ± 3%
V
TRIP
= 4.38V ± 3%
V
TRIP
= 2.85V ± 3%
V
TRIP
= 2.65V ± 3%
The summary of conditions for backup battery opera-
tion is given in Table 8:
Table 8. Battery Backup Operation
*since Vback>2.65V is higher than Vtrip, the battery is powering the entire device
2.7-5.5V
Supercapacitor
V
SS
V
CC
V
back
1. Example Application, Vcc = 5V, Vback = 3.0V
Condition Vcc Vback Vtrip Iback Reset Notes
a. Normal Operation 5.00 3.00 4.38 <<1µA H
b. Vcc on with no battery 5.00 0 4.38 0 H
c. Backup Mode 0-1.8 1.8-3.0 4.38 <2µA L Timekeeping
only
2. Example Application, Vcc=3.3V,Vback=3.0V
Condition Vcc Vback Vtrip Iback Reset
a. Normal Operation 3.30 3.00 2.65 <<1µA H
b. Vcc on with no battery 3.30 0 2.65 0 H
c. Backup Mode 0-1.8 1.8-3.0* 2.65 <2µA* L Timekeeping
only
d. UNWANTED - Vcc ON, Vback
powering
2.65 - 3.30 > Vcc 2.65 up to 3mA H Internal
Vcc = Vback
X1227
26
FN8099.2
May 8, 2006
Referring to Figure 20, Vtrip applies to the “Internal
Vcc” node which powers the entire device. This means
that if Vcc is powered down and the battery voltage at
Vback is higher than the Vtrip voltage, then the entire
chip will be running from the battery. If Vback falls to
lower than Vtrip, then the chip shuts down and all out-
puts are disabled except for the oscillator and time-
keeping circuitry. The fact that the chip can be
powered from Vback is not necessarily an issue since
standby current for the RTC devices is <2µA for this
mode (called “main timekeeping current” in the data
sheet). Only when the serial interface is active is there
an increase in supply current, and with Vcc powered
down, the serial interface will most likely be inactive.
One way to prevent operation in battery backup mode
above the Vtrip level is to add a diode drop (silicon
diode preferred) to the battery to insure it is below
Vtrip. This will also provide reverse leakage protection
which may be needed to get safety agency approval.
One mode that should always be avoided is the opera-
tion of the RTC device with Vback greater than both Vcc
and Vtrip (Condition 2d in Table 8). This will cause the
battery to drain quickly as serial bus communication and
non-volatile writes will require higher supplier current.
PERFORMANCE DATA
I
BACK
Performance
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
I
BACK
vs. Temperature
Multi-Lot Process Variation Data
Temperature °C
-40 25 60 85
I
BACK
(µA)
3.3V
1.8V
X1227
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FN8099.2
May 8, 2006
X1227
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1
L
L1
DETAIL X
4° ±4°
SEATING
PLANE
e
H
b
C
0.010 BM CA
0.004 C
0.010 BM CA
B
D
(N/2)
1
E1
E
NN
(N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL SO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28) TOLERANCE NOTES
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
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X1227V8I-2.7

Mfr. #:
Buy X1227V8I-2.7
Manufacturer:
Renesas / Intersil
Description:
IC RTC CLK/CALENDAR I2C 8-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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