OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

X1227V8I-2.7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
16
FN8099.2
May 8, 2006
Figure 5. Power-on Reset and Low Voltage Reset
V
CC
THRESHOLD RESET PROCEDURE
[OPTIONAL]
The X1227 is shipped with a standard V
CC
threshold
(V
TRIP
) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard V
TRIP
is not exactly right, or if
higher precision is needed in the V
TRIP
value, the
X1227 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvol-
atile write control signal.
Setting the V
TRIP
Voltage
It is necessary to reset the trip point before setting the
new value.
To set the new V
TRIP
voltage, apply the desired
V
TRIP
threshold voltage to the V
CC
pin and tie the
RESET
pin to the programming voltage V
P
. Then
write data 00h to address 01h. The stop bit following
a valid write operation initiates the V
TRIP
program-
ming sequence. Bring RESET
to V
CC
to complete the
operation. Note: this operation may take up to 10 mil-
liseconds to complete and also writes 00h to address
01h of the EEPROM array.
Figure 6. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
value)
Resetting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a “native”
voltage level. For example, if the current V
TRIP
is 4.4V
and the new V
TRIP
must be 4.0V, then the V
TRIP
must
be reset. When V
TRIP
is reset, the new V
TRIP
is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the new V
TRIP
voltage, apply more than 3.0V
to the V
CC
pin and tie the RESET pin to the
programming voltage V
P
. Then write 00h to address
03h. The stop bit of a valid write operation initiates the
V
TRIP
programming sequence. Bring RESET to V
CC
to
complete the operation. Note: this operation takes up
to 10 milliseconds to complete and also writes 00h to
address 03h of the EEPROM array.
For best accuracy in setting V
TRIP
, it is advised that
the following sequence be used.
1.Program V
TRIP
as above.
2.Measure resulting V
TRIP
by measuring the V
CC
value where a RESET
occurs. Calculate Delta =
(Desired - Measured) V
TRIP
value.
3.Perform a V
TRIP
program using the following formula
to set the voltage of the RESET
pin:
V
RESET
= (Desired Value – Delta) + 0.025V
V
CC
V
TRIP
RESET
t
PURST
t
PURST
t
R
t
F
t
RPD
V
RVALID
SCL
SDA
01h
RESET
V
P
= 15V
00h
01234567
01234567 01234567 01234567
AEh 00h
V
CC
V
CC
Note: BP0, BP1, BP2 must be disabled.
X1227
17
FN8099.2
May 8, 2006
Figure 7. Reset V
TRIP
Level Sequence
SERIAL COMMUNICATION
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 8.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 9.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the Standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus. See
Figure 9.
Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 10.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
– The 2nd Data Byte of a Status Register Write Oper-
ation (only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
01234567
SCL
SDA
AEh
01234567
03h
RESET
V
P
= 15V
00h
01234567 01234567
00h
V
CC
V
CC
Note: BP0, BP1, BP2 must be disabled.
X1227
18
FN8099.2
May 8, 2006
Figure 8. Valid Data Changes on the SDA Bus
Figure 9. Valid Start and Stop Conditions
Figure 10. Acknowledge Response From Receiver
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to either the EEPROM
array or to the CCR. Slave bits ‘1010’ access the
EEPROM array. Slave bits ‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the cus-
tomer to a known state.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the
operation to be performed. When this R/W
bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 11.
After loading the entire Slave Address Byte from the
SDA bus, the X1227 compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power-
up the internal address counter is set to address 0h,
so a current address read of the EEPROM array starts
at address 0. When required, as part of a random
read, the master must supply the 2 Word Address
Bytes as shown in Figure 11.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in
the “read” section. That is if the random read is from
the array the slave byte must be 1010111x in both
instances. Similarly, for a random read of the
Clock/Control Registers, the slave byte must be
1101111x in both places.
SCL
SDA
Data Stable Data Change Data Stable
SCL
SDA
Start Stop
SCL from
Master
Data Output
from Transmitter
Data Output
from Receiver
81 9
Start Acknowledge
X1227
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

X1227V8I-2.7

Mfr. #:
Buy X1227V8I-2.7
Manufacturer:
Renesas / Intersil
Description:
IC RTC CLK/CALENDAR I2C 8-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet