AD1937
Rev. B | Page 9 of 36
TIMING DIAGRAMS
t
DBH
DBCLK
DLRCLK
DSDATAx
LEFT-JUSTIFIED
MODE
DSDATAx
RIGHT-JUSTIFIED
MODE
DSDATAx
I
2
S-JUSTIFIED
MODE
t
DLH
t
DBL
t
DLS
t
DDS
MSB
MSB
MSB LSB
MSB – 1
t
DDH
t
DDS
t
DDH
t
DDS
t
DDH
t
DDS
t
DDH
07414-025
RIGHT-JUSTIFIED
MODE
Figure 2. DAC Serial Timing
ABCLK
ALRCLK
ASDATAx
LEFT-JUSTIFIED
MODE
ASDATAx
ASDATAx
I
2
S-JUSTIFIED
MODE
t
ABH
LSB
MSB
MSB
MSB – 1
MSB
t
ABL
t
ALS
t
ABDD
t
ABDD
t
ABDD
t
ALH
0
7414-026
Figure 3. ADC Serial Timing
AD1937
Rev. B | Page 10 of 36
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 9.
Parameter Rating
Analog (AVDD) −0.3 V to +3.6 V
Digital (DVDD) −0.3 V to +3.6 V
VSUPPLY −0.3 V to +6.0 V
Input Current (Except Supply Pins) ±20 mA
Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V
Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V
Operating Temperature Range (Case) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
θ
JA
represents junction-to-ambient thermal resistance;
θ
JC
represents the junction-to-case thermal resistance.
All characteristics are for a 4-layer board.
Table 10.
Package Type θ
JA
θ
JC
Unit
64-Lead LQFP 47 11.1 °C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD1937
Rev. B | Page 11 of 36
NC = NO CONNECT
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
64
NC
63
AVDD
62
LF
61
ADC2RN
60
ADC2RP
59
ADC2LN
58
ADC2LP
57
ADC1RN
56
ADC1RP
55
ADC1LN
54
ADC1LP
53
CM
52
AVDD
51
NC
50
NC
49
DVDD
17
DSDATA3
18
DSDATA2
19
DSDATA1
20
DBCLK
21
DLRCLK
22
VSUPPLY
23
VSENSE
24
VDRIVE
25
ASDATA2
26
ASDATA1
27
ABCLK
28
ALRCLK
29
ADDR0
30
SDA
31
AGND
1
DVDD
32
MCLKI/MCLKXI
2
MCLKO/MCLKXO
3
AGND
4
AVDD
5
DAC3LP
6
DAC3LN
7
DAC3RP
8
DAC3RN
9
DAC4LP
10
DAC4LN
11
DAC4RP
12
DAC4RN
13
PD/RST
14
AGND
48
FILTR
47
AGND
46
AVDD
45
AGND
44
DAC2RN
43
DAC2RP
42
DAC2LN
41
DAC2LP
40
DAC1RN
39
DAC1RP
38
DAC1LP
36
ADDR1
35
DSDATA4
15
SCL
34
DGND
16
DGND
33
DAC1LN
37
AD1937
TOP VIEW
(Not to Scale)
DIFFERENTIAL OUTPUT
07414-002
Figure 4. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. Type
1
Mnemonic Description
1, 4, 44, 46, 48 I AGND Analog Ground.
2 I MCLKI/MCLKXI Master Clock Input/Crystal Oscillator Input.
3 O MCLKO/MCLKXO Master Clock Output/Crystal Oscillator Output.
5, 45, 51, 62 I AVDD Analog Power Supply. Connect this pin to analog 3.3 V supply.
6 O DAC3LP DAC3 Left Positive Output.
7 O DAC3LN DAC3 Left Negative Output.
8 O DAC3RP DAC3 Right Positive Output.
9 O DAC3RN DAC3 Right Negative Output.
10 O DAC4LP DAC4 Left Positive Output.
11 O DAC4LN DAC4 Left Negative Output.
12 O DAC4RP DAC4 Right Positive Output.
13 O DAC4RN DAC4 Right Negative Output
14 I
PD
/RST
Power-Down Reset (Active Low).
15 I/O DSDATA4
DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line mode)/
AUX DAC2 data out (to external DAC2).
16, 33 I DGND Digital Ground.
17, 32 I DVDD Digital Power Supply. Connect this pin to digital 3.3 V supply.
18 I/O DSDATA3
DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line mode)/AUX
ADC2 data in (from external ADC2).
19 I/O DSDATA2
DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX ADC1 data in
(from external ADC1).
20 I DSDATA1 DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in.
21 I/O DBCLK Bit Clock for DACs. Can be programmed as input or output in all modes.
22 I/O DLRCLK Frame Clock for DACs. Can be programmed as input or output in all modes.

AD1937WBSTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs Single Chip Codec 4 s w/Diff Output
Lifecycle:
New from this manufacturer.
Delivery:
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