AD1937
Rev. B | Page 27 of 36
CONTROL REGISTERS
DEFINITIONS
The global address for the AD1937 is 0x08 OR’ed with ADDR1 and ADDR0 and one R/
W
bit; see and . The address
bits (Bits[18:17]) setting must correspond to the low/high state of Pin 30 and Pin 35. All registers are reset to 0, except for the DAC
volume registers that are set to full volume.
Figure 13 Figure 14
Note that the first setting in each control register parameter is the default setting.
Table 20. Register Format
Global Address R/
W
Register Address Data
Bit
23:17 16 15:8 7:0
Table 21. Register Addresses and Functions
Hexadecimal Address Function
0x00 0 PLL and Clock Control 0
0x01 1 PLL and Clock Control 1
0x02 2 DAC Control 0
0x03 3 DAC Control 1
0x04 4 DAC Control 2
0x05 5 DAC individual channel mutes
0x06 6 DAC1L volume control
0x07 7 DAC1R volume control
0x08 8 DAC2L volume control
0x09 9 DAC2R volume control
0x0A 10 DAC3L volume control
0x0B 11 DAC3R volume control
0x0C 12 DAC4L volume control
0x0D 13 DAC4R volume control
0x0E 14 ADC Control 0
0x0F 15 ADC Control 1
0x10 16 ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 22. PLL and Clock Control 0 Register (Address 0, 0x00)
Bit Value Function Description
0 0 Normal operation PLL power-down
1 Power-down
2:1 00 Input 256 (× 44.1 kHz or 48 kHz) MCLKI/MCLKXI pin functionality (PLL active), master clock rate setting
01 Input 384 (× 44.1 kHz or 48 kHz)
10 Input 512 (× 44.1 kHz or 48 kHz)
11 Input 768 (× 44.1 kHz or 48 kHz)
4:3 00 XTAL oscillator enabled MCLKO/MCLKXO pin, master clock rate setting
01 256 × f
S
VCO output
10 512 × f
S
VCO output
11 Off
6:5 00 MCLKI/MCLKXI PLL input
01 DLRCLK
10 ALRCLK
11 Reserved
7 0 Disable: ADC and DAC idle Internal master clock enable
1 Enable: ADC and DAC active
