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AD1937WBSTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
AD1937
Rev. B | Page 18 of 36
Table 13. I
2
C Abbreviation Table
Abbreviation Condition
S Repeated start by master
P Stop by master
AM Acknowledge by master
AS Acknowledge by AD1937
Table 14. Single Word I
2
C Write
S
Chip Address, R/W = 0
AS Register Address AS Data Word AS P
Table 15. Burst Mode I
2
C Write
S
Chip Address, R/W = 0
AS Register Address AS Data Word 1 AS Data Word 2 AS Data Word N AS P
Table 16. Single Word I
2
C Read
S
Chip Address, R/W = 0
AS Register Address AS S
Chip Address, R/W
= 1
AS
Data Word AM P
Table 17. Burst Mode I
2
C Read
S
Chip Address,
R/W
= 0
AS
Register
Address
AS S
Chip Address,
R/W
= 1
AS
Data
Word 1
AM
Data
Word 2
AM
Data
Word N
AM P
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1937 is designed for a 3.3 V supply. Separate power
supply pins are provided for the analog and digital sections.
To minimize noise pickup, these pins should be bypassed with
100 nF ceramic chip capacitors placed as close to the pins as
possible. A bulk aluminum electrolytic capacitor of at least
22 μF should also be provided on the same printed circuit
board (PCB) as the codec. For critical applications, improved
performance is obtained with separate supplies for the analog
and digital sections. If this is not possible, it is recommended
that the analog and digital load pins be isolated by means of a
ferrite bead in series with the supply. It is important that the
analog supply be as clean as possible.
The AD1937 includes a 3.3 V regulator driver that only requires
an external pass transistor, a resistor, and bypass capacitors to
turn a 5 V supply into 3.3 V. If the regulator driver is not used,
connect VSUPPLY, VDRIVE, and VSENSE to DGND.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
The ADC and DAC internal analog voltage reference (V
REF
) is
brought out on the FILTR pin and should be bypassed as close
as possible to the chip with a parallel combination of 10 μF and
100 nF capacitors. Any external current drawn should be limited
to less than 50 μA.
The internal reference can be disabled in the PLL and Clock
Control 1 register, and FILTR can be driven from an external
source. This can be used to scale the DAC output to the clipping
level of a power amplifier based on its power supply voltage.
The ADC input gain varies by the inverse ratio. It is not advisable
to drive the FILTR pin with more than (AVDD/2) V. The total
gain from ADC input to DAC output remains constant.
The CM pin should be bypassed as close as possible to the chip,
with a parallel combination of 47 μF and 100 nF capacitors. This
voltage can be used to bias external op amps to the common-mode
voltage of the input and output signal pins. The output current
should be limited to less than 0.5 mA source and 2 mA sink.
AD1937
Rev. B | Page 19 of 36
SERIAL DATA PORTS—DATA FORMAT
The eight DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The four ADC channels use a common serial bit
clock (ABCLK) and left-right framing clock (ALRCLK) in the
serial data port. The clock signals are all synchronous with the
sample rate. The normal stereo serial modes are shown in
Figure 15.
The ADC and DAC serial data modes default to I
2
S stereo.
The ports can also be programmed for left-justified stereo,
right-justified stereo, and TDM modes. The word width is
24 bits by default and can be set to 16 or 20 bits in the DAC
Control 2 and ADC Control 1 registers. The DAC serial formats
are programmable in the DAC Control 0 register. The polarity of
DBCLK and DLRCLK is programmable in the DAC Control 1 reg-
ister. The ADC serial format is programmable in ADC Control 1
register. The ABCLK and ALRCLK clock polarities are pro-
grammed in ADC Control 2 register. In Figure 2, Figure 3, and
Figure 15 all of the clocks are shown with their normal polarity.
Both DAC and ADC serial ports can be programmed to become
the bus masters according to DAC Control 1 and ADC Control 2
registers. By default, both ADC and DAC serial ports are in the
slave mode.
LRCLK
BCLK
SDAT
A
LRCLK
BCLK
SDAT
A
LRCLK
BCLK
SDAT
A
LSB LSB
LSB
LSB
LEFT CHANNEL RIGHT CHANNEL
LSB LSB
LEFT CHANNEL RIGHT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
MSB MSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
MSB
MSB
MSB MSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
I
2
S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LRCLK
BCLK
SDAT
A
LSB LSB
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT
f
S
EXCEPT FOR DSP MODE, WHICH IS 2 × f
S
.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
MSB MSB
1/
f
S
07414-024
Figure 15. Stereo Modes
AD1937
Rev. B | Page 20 of 36
TIME-DIVISION MULTIPLEXED (TDM) MODES
The serial ports of the AD1937 have several different TDM
serial data modes. Single-line TDM mode is the most com-
monly used configuration (see Figure 16 and Figure 17).
These figures show 8-channel configuration; other possible
options are 4- and 16-channel configurations. In Figure 16,
the eight on-chip DAC data slots are packed into one I
2
S
TDM stream. In this mode, both DBCLK and ABCLK are
256 f
S
. In Figure 17, the ADC serial port outputs one data
stream consisting of four on-chip ADCs followed by four
unused slots.
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2
MSB MSB – 1 MSB – 2 DATA
BCLK
LRCLK
SLOT 5
LEFT 3
SLOT 6
RIGHT 3
SLOT 7
LEFT 4
SLOT 8
RIGHT 4
DLRCLK
DBCLK
DSDATA
256 BCLKs
32 BCLKs
07414-014
Figure 16. Single-Line TDM Mode 8-Channel DAC Configuration
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2
MSB MSB – 1 MSB – 2 DATA
BCLK
LRCLK
SLOT 5 SLOT 6 SLOT 7 SLOT 8
ALRCLK
ABCLK
SDAT
256 BCLKs
32 BCLKs
07414-013
Figure 17. Single-Line TDM Mode 8-Channel ADC Configuration
The I/O pin functions of the serial ports are defined according
to the serial mode that is selected. For a detailed description of
the function of each pin in TDM and TDM/AUX modes, see
Table 18.
The AD1937 allows systems with more than eight DAC channels
to be easily configured by the use of an auxiliary serial data port.
The TDM/AUX mode 16-channel configuration is shown in
Figure 18. In this mode, the AUX channels are the last four
slots of the TDM data stream. These slots are extracted and
output to the AUX serial port. It should be noted that due to
the high DBCLK frequency, this mode is available only in the
48 kHz/44.1 kHz/32 kHz sample rates. An 8-channel DAC
configuration cannot be TDM/AUX because there are no
extra data slots for the AUX packets; this would be single-
line TDM mode.
The AD1937 also allows system configurations with more
than four ADC channels as shown in Figure 19 (using 8 ADCs)
and Figure 20 (using 16 ADCs). Due to the high ABCLK
frequency, this mode is available only in the 48 kHz/44.1 kHz/
32 kHz sample rates.
Combining the TDM/AUX ADC and DAC modes results in
a system configuration of 8 ADCs and 12 DACs. The system,
then consists of two external stereo ADCs, two external stereo
DACs, and one AD1937. This mode is shown in Figure 21
(combined TDM/AUX DAC and ADC modes).
In the TDM/AUX mode, the frame sync (ALRCLK) triggers
the TDM word by crossing the high frequency TDM BCLK
(ABCLK) to 0, similar to the single-line TDM modes (see
Figure 16 and Figure 17). The AUX LRCLK (DLRCLK) runs at
the much slower f
S
of the AUX port; the AUX BCLK (DBCLK)
runs at 64 × f
S
. This is shown in the TDM/AUX figures (see
Figure 18 to Figure 21).
Table 18. Pin Function Changes in TDM and TDM/AUX Modes
Mnemonic Stereo Modes TDM Modes TDM/AUX Modes
ASDATA1 ADC1 data out TDM ADC data out TDM data out
ASDATA2 ADC2 data out TDM ADC data in AUX DAC1 data out (to external DAC1)
DSDATA1 DAC1 data in TDM DAC data in
TDM data in
DSDATA2 DAC2 data in TDM DAC data out
AUX ADC1 data in (from external ADC1)
DSDATA3 DAC3 data in TDM DAC2 data in (dual-line mode)
AUX ADC2 data in (from external ADC2)
DSDATA4 DAC4 data in TDM DAC2 data out (dual-line mode)
AUX DAC2 data out (to external DAC2)
ALRCLK ADC LRCLK in/out TDM ADC frame sync in/out
TDM frame sync in/out
ABCLK ADC BCLK in/out TDM ADC BCLK in/out
TDM BCLK in/out
DLRCLK DAC LRCLK in/out TDM DAC frame sync in/out
AUX LRCLK in/out
DBCLK DAC BCLK in/out TDM DAC BCLK in/out AUX BCLK in/out
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

AD1937WBSTZ

Mfr. #:
Buy AD1937WBSTZ
Manufacturer:
Analog Devices Inc.
Description:
Interface - CODECs Single Chip Codec 4 s w/Diff Output
Lifecycle:
New from this manufacturer.
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