AD1937
Rev. B | Page 12 of 36
Pin No. Type
1
Mnemonic Description
23 I VSUPPLY 5 V Input to Regulator, Emitter of Pass Transistor.
24 I VSENSE Connect 3.3 V Regulator Output, Collector of Pass Transistor, to This Pin.
25 O VDRIVE Drive for Base of Pass Transistor.
26 I/O ASDATA2
ADC Serial Data Output 2. Data Output from ADC2/TDM ADC data in/AUX DAC1 data out (to
external DAC1).
27 O ASDATA1 ADC Serial Data Output 1. Data Output from ADC1/TDM ADC data out/TDM data out.
28 I/O ABCLK Bit Clock for ADCs. Can be programmed as input or output in all modes.
29 I/O ALRCLK Frame Clock for ADCs. Can be programmed as input or output in all modes.
30 I ADDR0 I
2
C Address Assignment.
31 I/O SDA Control Data Port (I
2
C).
34 I SCL Control Clock Port (I
2
C).
35 I ADDR1 I
2
C Address Assignment.
36 O DAC1LP DAC1 Left Positive Output.
37 O DAC1LN DAC1 Left Negative Output.
38 O DAC1RP DAC1 Right Positive Output.
39 O DAC1RN DAC1 Right Negative Output.
40 O DAC2LP DAC2 Left Positive Output.
41 O DAC2LN DAC2 Left Negative Output.
42 O DAC2RP DAC2 Right Positive Output.
43 O DAC2RN DAC2 Right Negative Output.
47 O FILTR Analog Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.
49, 50, 63, 64 NC No Connect.
52 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND.
53 I ADC1LP ADC1 Left Positive Input.
54 I ADC1LN ADC1 Left Negative Input.
55 I ADC1RP ADC1 Right Positive Input.
56 I ADC1RN ADC1 Right Negative Input.
57 I ADC2LP ADC2 Left Positive Input.
58 I ADC2LN ADC2 Left Negative Input.
59 I ADC2RP ADC2 Right Positive Input.
60 I ADC2RN ADC2 Right Negative Input.
61 O LF PLL Loop Filter, Return to AVDD.
1
I = input, O = output.
