CY62167DV30 MoBL
®
16-Mbit (1 M × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05328 Rev. *M Revised November 19, 2014
16-Mbit (1 M × 16) Static RAM
Features
■ Thin small outline package (TSOP-I) configurable as
1 M × 16 or as 2 M × 8 SRAM
■ Wide voltage range: 2.2 V–3.6 V
■ Ultra-low active power:
Typical active current: 2 mA at f = 1 MHz
■ Ultra-low standby power
■ Easy memory expansion with CE
1
, CE
2
and OE features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed / power
■ Available in Pb-free and non Pb-free 48-ball very fine-pitch ball
grid array (VFBGA) and 48-pin TSOP I package
Functional Description
The CY62167DV30 is a high-performance CMOS static RAM
organized as 1M words by 16-bits. This device features
advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL
) in portable
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption by 99% when addresses are not toggling. The
device can also be put into standby mode when deselected (CE
1
HIGH or CE
2
LOW or both BHE and BLE are HIGH). The
input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when: deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled (OE HIGH), both Byte High Enable
and Byte Low Enable are disabled (BHE
, BLE HIGH), or during
a Write operation (CE
1
LOW, CE
2
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If
Byte Low Enable (BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the address
pins (A
0
through A
19
). If Byte High Enable (BHE) is LOW, then
data from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip Enables
(CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while
forcing the Write Enable (WE
) HIGH. If Byte Low Enable (BLE)
is LOW, then data from the memory location specified by the
address pins appear on I/O
0
to I/O
7
. If Byte High Enable (BHE)
is LOW, then data from memory appear on I/O
8
to I/O
15
. See the
truth table at the back of this data sheet for a complete
description of Read and Write modes.
For a complete list of related documentation, click here.
1M × 16 / 2M x 8
RAM Array
I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
18
A
10
Power-Down
Circuit
BHE
BLE
CE
2
CE
1
CE
2
CE
1
A
19
BYTE
Logic Block Diagram
