24.The internal Write time of the memory is defined by the overlap of WE
, CE
1
= V
IL
, BHE and/or BLE = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the Write.
25.Data I/O is high-impedance if OE
= V
IH.
26.If CE
1
goes HIGH and CE
2
goes LOW simultaneously with WE = V
IH
, the output remains in a high-impedance state.
27.During this period, the I/Os are in output state and input signals should not be applied.
CY62167DV30 MoBL
®
Document Number: 38-05328 Rev. *M Page 11 of 18
Figure 10. Write Cycle 4 (BHE
/BLE Controlled, OE LOW)
[28]
Switching Waveforms(continued)
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
VALID DATA
t
BW
t
SCE
t
PWE
Note 29
DATA I/O
ADDRESS
CE
1
WE
BHE/BLE
CE
2
Notes
28.If CE
1
goes HIGH and CE
2
goes LOW simultaneously with WE = V
IH
, the output remains in a high-impedance state.
29.During this period, the I/Os are in output state and input signals should not be applied.
