CY28346ZXC Datasheet CY28346OXC, CY28346ZXCT, CY28346ZXC | P1-P3

Clock Synthesizer with Differential CPU Outputs

CY28346

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 38-07331 Rev. *C Revised March 11, 2005

Features

• Compliant with Intel

CK 408 Mobile Clock Synthesizer

specifications

• 3.3V power supply

• Three differential CPU clocks

• Ten copies of PCI clocks

• 5/6 copies of 3V66 clocks

• SMBus support with read-back capabilities

• Spread Spectrum electromagnetic interference (EMI)

reduction

• Dial-a-Frequency™ features

• Dial-a-dB™ features

• 56-pin TSSOP and SSOP packages

Table 1. Frequency Table

[1]

S2 S1 S0 CPU (0:2) 3V66

66BUFF(0:2)/

3V66(0:4) 66IN/3V66–5 PCI_FPCI REF

USB/

DOT

1 0 0 66M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M

1 0 1 100M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M

1 1 0 200M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M

1 1 1 133M 66M 66IN 66-MHZ clock input 66IN/2 14.318M 48M

0 0 0 66M 66M 66M 66M 33 M 14.318M 48M

0 0 1 100M 66M 66M 66M 33 M 14.318M 48M

0 1 0 200M 66M 66M 66M 33 M 14.318M 48M

0 1 1 133M 66M 66M 66M 33 M 14.318M 48M

M 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

M 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2

Note:

1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a

0 state will be latched into the device’s internal state register.

PLL1

PLL2

Logic

Power

Up Logic

XIN

XOUT

CPU_STP#

IREF

VSSIREF

S(0:2)

MULT0

VTT_PG#

PCI_STP#

PD#

SDATA

SCLK

VDDA

66B[0:2]/3V66[2:4]

48M DOT

48M USB

PCI_F(0:2)

PCI(0:6)

3V66_1/VCH

3V66_0

CPUC(0:2)

CPUT(0:2)

REF

66IN/3V66-5

I2C

Logic

VDD

XIN

XOUT

VSS

PCIF0

PCIF1

PCIF2

VDD

VSS

PCI0

PCI1

PCI2

PCI3

VDD

VSS

PCI4

PCI5

PCI6

VDD

VSS

66B0/3V66_2

66B1/3V66_3

66B2/3V66_4

66IN/3V66_5

PD#

VDDA

VSSA

VTT_PG#

REF

CPU_STP#

CPUT0

CPUC0

VDD

CPUT1

CPUC1

VSS

VDD

CPUT2

CPUC2

MULT0

IREF

VSSIREF

48MUSB

48MDOT

VDD

VSS

3V66_1/VCH

PCI_STP#

3V66_0

VDD

VSS

SCLK

SDATA

CY28346

Pin ConfigurationBlock Diagram

CY28346

Document #: 38-07331 Rev. *C Page 2 of 20

Pin Description

Pin Name PWR I/O Description

2XIN IOscillator Buffer Input. Connect to a crystal or to an external clock.

3XOUTV

O Oscillator Buffer Output. Connect to a crystal. Do not connect when an external

clock is applied at X

52, 51, 49, 48,

45, 44

CPUT(0:2),

CPUC(0:2)

O Differential Host Output Clock Pairs. See Table 1 for frequency/functionality.

10, 11, 12, 13,

16, 17, 18

PCI(0:6) V

DDP

O PCI Clock Outputs. Are synchronous to 66IN or 3V66 clock. See Table 1 .

5, 6, 7 PCIF (0:2) V

O 33-MHz PCI Clocks. ÷2 copies of 66IN or 3V66 clocks that may be free running

(not stopped when PCI_STP# is asserted LOW) or may be stoppable depending

on the programming of SMBus register Byte3,Bits (3:5).

56 REF V

O Buffered Output Copy of the Device’s X

Clock.

42 IREF V

I Current Reference Programming Input for CPU Buffers. A resistor is

connected between this pin and VSSIREF.

28 VTT_PG# V

I Qualifying Input that Latches S(0:2) and MULT0. When this input is at a logic

LOW, the S(0:2) and MULT0 are latched.

39 48MUSB V

DD48

O Fixed 48-MHz USB Clock Outputs.

38 48MDOT V

DD48

O Fixed 48-MHZ DOT Clock Outputs.

33 3V66_0 V

O 3.3V 66-MHz Fixed-frequency Clock.

35 3V66_1/VCH V

O 3.3V Clock Selectable with SMBus Byte0,Bit5, When Byte5,Bit5. When Byte

0,Bit 5 is at a logic 1, then this pin is a 48M output clock. When Byte0,Bit5 is a

logic 0, this is a 66M output clock (default).

25 PD# V

Power-down Mode Pin. A logic LOW level causes the device to enter a

power-down state. All internal logic is turned off except for the SMBus logic. All

output buffers are stopped.

43 MULT0 I

Programming Input Selection for CPU Clock Current Multiplier.

55, 54 S(0,1) I I Frequency Select Inputs. See Table 1.

29 SDATA I I Serial Data Input. Conforms to the SMBus specification of a Slave

Receive/Transmit device. It is an input when receiving data. It is an open drain

output when acknowledging or transmitting data.

30 SCLK I I Serial Clock Input. Conforms to the SMBus specification.

40 S2 V

Frequency Select Input. See Table 1. This is a Tri-level input which is driven

HIGH, LOW or driven to a intermediate level.

34 PCI_STP# V

PCI Clock Disable Input. When asserted LOW, PCI (0:6) clocks are synchro-

nously disabled in a LOW state. This pin does not effect PCIF (0:2) clocks’

outputs if they are programmed to be PCIF clocks via the device’s SMBus

interface.

53 CPU_STP# V

CPU Clock Disable Input. When asserted LOW, CPUT (0:2) clocks are

synchronously disabled in a HIGH state and CPUC(0:2) clocks are synchro-

nously disabled in a LOW state.

24 66IN/3V66_5 V

I/O Input Connection for 66CLK(0:2) Output Clock Buffers if S2 = 1, or output

clock for fixed 66-MHz clock if S2 = 0. See Table 1.

21, 22, 23 66B(0:2)/

3V66(2:4)

O 3.3V Clock Outputs. These clocks are buffered copies of the 66IN clock or fixed

at 66 MHz. See Ta ble 1.

1, 8, 14, 19, 32,

37, 46, 50

PWR 3.3V Power Supply.

4, 9, 15, 20, 27,

31, 36, 47

PWR Common Ground.

41 V

IREF PWR Current Reference Programming Input for CPU Buffers. A resistor is

connected between this pin and IREF. This pin should also be returned to device

26 V

DDA

–PWRAnalog Power Input. Used for phase-locked loops (PLLs) and internal analog

circuits. It is also specifically used to detect and determine when power is at an

acceptable level to enable the device to operate.

CY28346

Document #: 38-07331 Rev. *C Page 3 of 20

Two-Wire SMBus Control Interface

The two-wire control interface implements a Read/Write slave

only interface according to SMBus specification.

The device will accept data written to the D2 address and data

may read back from address D3. It will not respond to any

other addresses, and previously set control registers are

retained as long as power in maintained on the device.

Serial Control Registers

Following the acknowledge of the Address Byte, two additional

bytes must be sent:

1. “Command code” byte

2. “Byte count” byte.

Although the data (bits) in the command is considered “don’t

care,” it must be sent and will be acknowledged. After the

Command Code and the Byte Count have been acknowl-

edged, the sequence (Byte 0, Byte 1, and Byte 2) described

below will be valid and acknowledged.

Byte 0

: CPU Clock Register

[2,3]

Bit @Pup Pin# Description

7 0 Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On

This is a Read and Write control bit.

6 0 CPU Clock Power-down Mode Select. 0 = Drive CPUT(0:2) to 4 or 6 IREF and drive

CPUC(0:2) LOW when PD# is asserted LOW. 1 = Tri-state all CPU outputs. This is only

applicable when PD# is LOW. It is not applicable to CPU_STP#.

5 0 35 3V66_1/VCH Frequency Select, 0 = 66M selected, 1 = 48M selected

This is a Read and Write control bit.

4 Pin 53 44,45,48,49,5

1,52

CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is

Read-only.

3 Pin 34 10,11,12,13,16

,17,18

Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP#

is a logical AND function of the internal SMBus register bit and the external PCI_STP# pin.

2 Pin 40 Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read-only.

1 Pin 55 Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read-only.

0 Pin 54 Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read-only.

Byte 1

: CPU Clock Register

Bit @Pup Pin# Description

7 Pin 43 43 MULT0 (Pin 43) Value. This bit is Read-only.

6 0 53 CPUT/C(0:2) Output Functionality Control When CPU_STP# is Asserted. 0 = Drive

CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) LOW when CPU_STP# asserted LOW.

1 = three-state all CPU outputs. This bit will override Byte0,Bit6 such that even if it is 0,

when PD# goes LOW the CPU outputs will be three-stated.

5 0 44,45 CPU2 Functionality Control When CPU_STP# is Asserted LOW. 1 = Free Running, 0 =

Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit.

4 0 48,49 CPU1 Functionality Control When CPU_STP# is Asserted LOW. 1 = Free Running, 0 =

Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit.

3 0 51,52 CPUT0 Functionality Control When CPU_STP# is Asserted LOW. 1 = Free Running, 0 =

Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit.

2 1 44,45 CPUT/C2 Output Control. 1 = enabled, 0 = disable HIGH and CPUC2 disables LOW. This

is a Read and Write control bit.

1 1 48,49 CPUT/C1 Output Control. 1 = enabled, 0 = disable HIGH and CPUC1 disables LOW. This

is a Read and Write control bit.

0 1 51,52 CPUT/C0 Output Control. 1 = enabled, 0 = disable HIGH and CPUC0 disables LOW. This

is a Read and Write control bit.

Notes:

2. PU = internal pull-up. PD = internal pull-down. T = tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 – 1.8V and HIGH = > 2.0V.

3. The “Pin#” column lists the relevant pin number where applicable. The “@Pup” column gives the default state at power-up.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

CY28346ZXC

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Description:

IC CLK FREQ SYNC CPU 200MHZ

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CY28346ZXC

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