CY28346ZXC Datasheet CY28346OXC, CY28346ZXCT, CY28346ZXC | P4-P6

CY28346

Document #: 38-07331 Rev. *C Page 4 of 20

Byte 2: PCI Clock Control Register (all bits are Read and Write functional)

Bit @Pup Pin# Description

7 0 53 REF Output Control. 0 = high strength, 1 = low strength.

6 1 18 PCI6 Output Control. 1 = enabled, 0 = forced LOW.

5 1 17 PCI5 Output Control. 1 = enabled, 0 = forced LOW.

4 1 16 PCI4 Output Control. 1 = enabled, 0 = forced LOW.

3 1 13 PCI3 Output Control. 1 = enabled, 0 = forced LOW.

2 1 12 PCI2 Output Control. 1 = enabled, 0 = forced LOW.

1 1 11 PCI1 Output Control. 1 = enabled, 0 = forced LOW.

0 1 10 PCI0 Output Control. 1 = enabled, 0 = forced LOW.

Byte 3

: PCI_F Clock and 48M Control Register (all bits are Read and Write functional)

Bit @Pup Pin# Description

7 1 38 48MDOT Output Control. 1 = enabled, 0 = forced LOW.

6 1 39 48MUSB Output Control. 1 = enabled, 0 = forced LOW.

5 0 7 PCI_STP#, Control of PCI_F2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.

4 0 6 PCI_STP#, Control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.

3 0 5 PCI_STP#, Control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW.

2 1 7 PCI_F2 Output Control. 1 = running, 0 = forced LOW.

1 1 6 PCI_F1 Output Control. 1 = running, 0 = forced LOW.

0 1 5 PCI_F0 Output Control. 1 = running, 0 = forced LOW.

Byte 4

: DRCG Control Register (all bits are Read and Write functional)

Bit @Pup Pin# Description

7 0 SS2 Spread Spectrum Control Bit (0 = down spread, 1 = center spread).

6 0 Reserved. Set = 0.

5 1 33 3V66_0 Output Enabled. 1 = enabled, 0 = disable.

4 1 35 3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled.

3 1 24 3V66_5 Output Enable. 1 = enabled, 0 = disabled.

2 1 23 66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled.

1 1 22 66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled.

0 1 21 66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled.

Byte 5

: Clock Control Register (all bits are Read and Write functional)

Bit @Pup Pin# Description

7 0 SS1 Spread Spectrum Control Bit.

6 1 SS0 Spread Spectrum Control Bit.

5 0 66IN to 66M delay Control MSB.

4 0 66IN to 66M delay Control LSB.

3 0 Reserved. Set = 0.

2 0 48MDOT Edge Rate Control. When set to 1, the edge is slowed by 15%.

1 0 Reserved. Set = 0.

0 0 USB edge rate control. When set to 1, the edge is slowed by 15%.

CY28346

Document #: 38-07331 Rev. *C Page 5 of 20

Byte 6: Silicon Signature Register

[4]

(all bits are Read-only)

Bit @Pup Pin# Description

7 0 Revision = 0001

3 0 Vendor Code = 0011

Byte 7

: Reserved Register

Bit @Pup Pin# Description

7 0 Reserved. Set = 0.

6 0 Reserved. Set = 0.

5 0 Reserved. Set = 0.

4 0 Reserved. Set = 0.

3 0 Reserved. Set = 0.

2 0 Reserved. Set = 0.

1 0 Reserved. Set = 0.

0 0 Reserved. Set = 0.

Byte 8

: Dial-a-Frequency Control Register N

Bit @Pup Name Description

7 0 Reserved. Set = 0.

6 0 N6, MSB These bits are for programming the PLL’s internal N register. This access allows the user to

modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks

(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios

relative to the CPU clock.

50N5

40N4

30N3

20N2

10N3

00N0, LSB

Byte 9

: Dial-a-Frequency Control Register R

Bit @Pup Name Description

70 Reserved. Set = 0.

6 0 R5, MSB These bits are for programming the PLL’s internal R register. This access allows the user to

modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks

(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios

relative to the CPU clock.

50R4

40R3

30R2

20R1

10R0

DAF_ENB R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded

from DAF (SMBus) registers.

Note:

4. When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.

CY28346

Document #: 38-07331 Rev. *C Page 6 of 20

Dial-a-Frequency Features

SMBus Dial-a-Frequency feature is available in this device via

Byte8 and Byte9.

P is a large-value PLL constant that depends on the frequency

selection achieved through the hardware selectors (S1, S0). P

value may be determined from Table 2.

Dial-a-dB Features

SMBus Dial-a-dB feature is available in this device via Byte8

and Byte9.

Spread Spectrum Clock Generation (SSCG)

Spread Spectrum is a modulation technique used to

minimizing EMI radiation generated by repetitive digital

signals. A clock presents the greatest EMI energy at the center

frequency it is generating. Spread Spectrum distributes this

energy over a specific and controlled frequency bandwidth

therefore causing the average energy at any one point in this

band to decrease in value. This technique is achieved by

modulating the clock away from its resting frequency by a

certain percentage (which also determines the amount of EMI

reduction). In this device, Spread Spectrum is enabled by

setting specific register bits in the SMBus control bytes.

Table 3 is a listing of the modes and percentages of Spread

Spectrum modulation that this device incorporates.

Test and Measurement Set-up

For Differential CPU Output Signals

The following diagram shows lumped test load configurations

for the differential Host Clock Outputs.

Table 2. P Value

S(1:0) P

0 0 32005333

0 1 48008000

1 0 96016000

1 1 64010667

Table 3. Spread Spectrum

SS2 SS1 SS0 Spread Mode Spread%

0 0 0 Down +0.00, –0.25

0 0 1 Down +0.00, –0.50

0 1 0 Down +0.00, –0.75

0 1 1 Down +0.00, –1.00

1 0 0 Center +0.13, –0.13

1 0 1 Center +0.25, –0.25

1 1 0 Center +0.37, –0.37

1 1 1 Center +0.50, –1.50

Measurement Point

2pF

CPUT

MULTSEL

PCB

CPUC

220Ω

63.4Ω

475Ω

33.2Ω

Measurement Point

2pF

Figure 1. 1.0V Test Load Termination

CPUT

MULTSEL

PCB

CPUC

33Ω

Measurement Point

49.9Ω

2pF

Measurement Point

2pF

475Ω

VDD

Figure 2. 0.7V Test Load Termination

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

CY28346ZXC

Mfr. #:

Buy CY28346ZXC

Manufacturer:

Cypress Semiconductor

Description:

IC CLK FREQ SYNC CPU 200MHZ

Lifecycle:

New from this manufacturer.

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CY28346ZXC

CY28346ZXC

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