CY28346ZXC Datasheet CY28346OXC, CY28346ZXCT, CY28346ZXC | P16-P18

CY28346

Document #: 38-07331 Rev. *C Page 16 of 20

66B

66B(0:2) Duty Cycle 45 55 45 55 45 55 45 55 % 12, 13

66B(0:2) Rise and Fall

Times

0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 12, 25

SKEW

Any 66B to Any 66B

Skew

175 175 175 175 ps 12, 13

66IN to 66B(0:2) Propa-

gation Delay

2.5 4.5 2.5 4.5 2.5 4.5 2.5 4.5 ns 12, 13

CCJ

66B(0:2) Cycle to Cycle

Jitter

100 100 100 100 ps 12, 13,

PCI

PCI_F(0:2) PCI (0:6)

Duty Cycle

45 55 45 55 45 55 45 55 % 12, 13

PERIOD

PCI_F(0:2) PCI (0:6)

Period

30.0 30.0 30.0 30 nS 9, 12, 13

HIGH

PCI_F(0:2) PCI (0:6)

HIGH Time

12.0 12.0 12.0 12.0 nS 23

LOW

PCI_F(0:2) PCI (0:6)

LOW Time

12.0 12.0 12.0 12.0 nS 24

PCI_F(0:2) PCI (0:6)

Rise and Fall Times

0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 nS 25

SKEW

Any PCI Clock to Any

PCI Clock Skew

500 500 500 500 pS 12, 13

CCJ

PCI_F(0:2) PCI (0:6)

Cycle to Cycle Jitter

250 250 250 250 ps 12, 13

48MUSB

48MUSB Duty Cycle 45 55 45 55 45 55 45 55 % 12, 13

PERIOD

48MUSB Period 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 12, 13

48MUSB Rise and Fall

Times

1.0 2.0 1.0 2.0 1.0 2.0 1.0 2.10 ns 12, 25

CCJ

48MUSB Cycle to Cycle

Jitter

350 350 350 350 ps 9, 12, 13

48MDOT

48MDOT Duty Cycle 45 55 45 55 45 55 45 55 % 12, 13

PERIOD

48MDOT Period 20.837 20.837 20.837 20.837 ns 12, 13

48MDOT Rise and Fall

Times

0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 ns 12, 13

CCJ

48MDOT Cycle to Cy-

cle Jitter

350 350 350 350 ps 12, 13

REF

REF Duty Cycle 4555 455545554555%12, 13

PERIOD

REF Period 69.84 71.0 69.84 71.0 69.84 71.0 69.84 71.0 ns 12, 13

REF Rise and Fall

Times

1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns 12, 25

CCJ

REF Cycle to Cycle

Jitter

1000 1000 1000 1000 ps 12, 13

Note:

26. This figure is in addition to any jitter already present when the 66IN pin is being used as an input. Otherwise a 500-ps jitter figure is specified.

AC Parameters (V

= V

DDA

= 3.3V ±5%, T

= 0°C to +70°C) (continued)

Parameter Description

66 MHz 100 MHz 133 MHz 200 MHz

Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.

CY28346

Document #: 38-07331 Rev. *C Page 17 of 20

PZL

PZH

Output Enable Delay

(All Outputs)

1.0 10.0 1.0 10.0 1.0 10.0 1.0 10.0 ns 10

PZL

PZH

Output disable delay (all

outputs)

1.0 10.0 1.0 10.0 1.0 10.0 1.0 10.0 ns 10

STABLE

All Clock Stabilization

from Power-up

3333ms10

Stopclock Set-up Time 10.0 10.0 10.0 10.0 ns 27

Stopclock Hold Time 0 0 0 0 ns 27

Oscillator Start-up Time X X X X ms 28

AC Parameters (V

= V

DDA

= 3.3V ±5%, T

= 0°C to +70°C) (continued)

Parameter Description

66 MHz 100 MHz 133 MHz 200 MHz

Unit NotesMin. Max. Min. Max. Min. Max. Min. Max.

Table 9. Maximum Lumped Capacitive Output Loads

Clock Max. Load Units

PCI Clocks 30 pF

3V66 (0,1) 30 pF

66B(0:2) 30 pF

48MUSB Clock 20 pF

48MDOT 10 pF

REF Clock 50 pF

Notes:

27. CPU_STP# and PCI _STP# set-up time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next PCI_F clock’s rising edge

28. When crystal meets minimum 40Ω device series resistance specification.

29. Device is not affected, VTT_PWRGD# is ignored.

VID (0:3),

SEL (0,1)

VTT_PWRGD#

PWRGD

VDD Clock Gen

Clock State

Clock Outputs

Clock VCO

0.2-0.3mS

Delay

State 0

State 2 State 3

Wait for

VTT_GD#

Sample Sels

Off

State 1

(Note A)

Figure 16. VTT_PWRGD# Timing Diagram29

[29]

CY28346

Document #: 38-07331 Rev. *C Page 18 of 20

Ordering Information

Part Number Package Type Product Flow

CY28346OC 56-pin SSOP – Tube Commercial, 0° to 70°C

CY28346OCT 56-pin SSOP – Tape and Reel Commercial, 0

° to 70°C

CY28346ZC 56-pin TSSOP – Tube Commercial, 0

° to 70°C

CY28346ZCT 56-pin TSSOP – Tape and Reel Commercial, 0

° to 70°C

Lead-free

CY28346OXC 56-pin SSOP – Tube Commercial, 0° to 70°C

CY28346OXCT 56-pin SSOP – Tape and Reel Commercial, 0

° to 70°C

CY28346ZXC 56-pin TSSOP – Tube Commercial, 0

° to 70°C

CY28346ZXCT 56-pin TSSOP – Tape and Reel Commercial, 0

° to 70°C

Delay 0.25mS

Power Off

VDDA = 2.0V

Sample

Inputs (pins

54,55)

VDD3.3 = Off

Normal

Operation

Enable Outputs

Figure 17. Clock Generator Power-up/Run State Diagram

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

CY28346ZXC

Mfr. #:

Buy CY28346ZXC

Manufacturer:

Cypress Semiconductor

Description:

IC CLK FREQ SYNC CPU 200MHZ

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

CY28346ZXC

CY28346ZXC

Products related to this Datasheet