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71V67703S75BQG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
6.4216
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 - Byte Controlled
(1,2,3)
A
D
D
R
E
S
S
C
L
K
A
D
S
P
A
D
S
C
t
C
Y
C
t
S
S
t
H
S
t
C
H
t
C
L
t
H
A
t
S
A
A
x
A
y
t
H
W
B
W
x
A
D
V
D
A
T
A
O
U
T
O
E
t
H
C
t
S
D
S
i
n
g
l
e
W
r
i
t
e
B
u
r
s
t
W
r
i
t
e
I
1
(
A
x
)
I
2
(
A
y
)
I
2
(
A
y
)
I
2
(
A
z
)
t
H
D
B
u
r
s
t
R
e
a
d
E
x
t
e
n
d
e
d
B
u
r
s
t
W
r
i
t
e
t
O
H
Z
D
A
T
A
I
N
t
S
A
V
t
S
W
O
4
(
A
w
)
C
E
,
C
S
1
t
H
W
B
W
E
t
S
W
(
N
o
t
e
3
)
I
1
(
A
z
)
A
z
I
4
(
A
y
)
I
1
(
A
y
)
I
4
(
A
y
)
I
3
(
A
y
)
t
S
C
B
W
E
i
s
i
g
n
o
r
e
d
w
h
e
n
A
D
S
P
i
n
i
t
i
a
t
e
s
a
c
y
c
l
e
a
n
d
i
s
s
a
m
p
l
e
d
o
n
t
h
e
n
e
x
t
c
y
c
l
e
r
i
s
i
n
g
e
d
g
e
B
W
x
i
s
i
g
n
o
r
e
d
w
h
e
n
A
D
S
P
i
n
i
t
i
a
t
e
s
a
c
y
c
l
e
a
n
d
i
s
s
a
m
p
l
e
d
o
n
t
h
e
n
e
x
t
c
l
o
c
k
r
i
s
i
n
g
e
d
g
e
I
3
(
A
z
)
O
3
(
A
w
)
5
3
0
9
d
r
w
0
9
(
A
D
V
H
I
G
H
s
u
s
p
e
n
d
s
b
u
r
s
t
)
,
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external address
Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS
0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
17
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
t
C
Y
C
t
S
S
t
C
L
t
C
H
t
H
A
t
S
A
t
S
C
t
H
C
t
O
E
t
O
L
Z
t
H
S
C
L
K
A
D
S
P
A
D
S
C
A
D
D
R
E
S
S
G
W
C
E
,
C
S
1
A
D
V
D
A
T
A
O
U
T
O
E
Z
Z
S
i
n
g
l
e
R
e
a
d
S
n
o
o
z
e
M
o
d
e
t
Z
Z
P
W
5
3
0
9
d
r
w
1
3
O
1
(
A
x
)
A
x
(
N
o
t
e
4
)
t
Z
Z
R
A
z
,
NOTES:
1. Device must power up in deselected Mode.
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS
0 timing transitions are identical but inverted to the CE and CS1 signaals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Waveform of Sleep (ZZ) and Power-Down Modes
(1,2,3)
6.4218
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
GW, BWE, BWx
CE, CS
1
CS
0
ADDRESS
ADSC
DATA
OUT
OE
Av Aw Ax Ay Az
(Av) (Aw) (Ax) (Ay)
5309 drw 10
,
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
GW
CE, CS
1
CS
0
ADDRESS
ADSC
DATA
IN
Av Aw Ax AzAy
(Av) (Aw) (Ax) (Az)(Ay)
5309 drw 11
,
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

71V67703S75BQG

Mfr. #:
Buy 71V67703S75BQG
Manufacturer:
IDT
Description:
SRAM 9M 3.3V PBSRAM SLOW F/T
Lifecycle:
New from this manufacturer.
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