PCA85176 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 7 April 2015 25 of 60
NXP Semiconductors
PCA85176
40 x 4 automotive LCD driver for low multiplex rates
7.6.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 15 (see Figure 13 as
well).
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 16
.
In the case described in Table 16 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to segments/elements on the display. This can be
achieved by a combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written
• The data-pointer (see Section 7.6.1 on page 24) has to be set to the address of bit a1
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6
• The data-pointer has to be set to the address of bit b1
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some segments/elements remain unused or can be used, but it has to be considered in
the module layout process as well as in the driver software design.
Table 15. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any segments/elements on the
display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0 1 2 3 4 5 6 7 8 9 :
0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 :
1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 :
2 a5 a2 - b5 b2 - c5 c2 - d5 :
3 ----------:
Table 16. Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to segments/elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0 1 2 3 4 5 6 7 8 9 :
0 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 :
1 a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 :
2 a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 :
3 ----------:
