PCA85176 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 7 April 2015 31 of 60
NXP Semiconductors
PCA85176
40 x 4 automotive LCD driver for low multiplex rates
8.5 I
2
C-bus controller
The PCA85176 acts as an I
2
C-bus slave receiver. It does not initiate I
2
C-bus transfers or
transmit data to an I
2
C-bus master receiver. The only data output from the PCA85176 are
the acknowledge signals of the selected devices. Device selection depends on the
I
2
C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to V
SS
which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to V
SS
or V
DD
using a binary coding scheme, so that
no two devices with a common I
2
C-bus slave address have the same hardware
subaddress.
8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.7 I
2
C-bus protocol
Two I
2
C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCA85176. The entire I
2
C-bus slave address byte is shown in Table 17.
The PCA85176 is a write-only device and will not respond to a read access, therefore bit 0
should always be logic 0. Bit 1 of the slave address byte that a PCA85176 will respond to,
is defined by the level tied to its SA0 input (V
SS
for logic 0 and V
DD
for logic 1).
Having two reserved slave addresses allows the following on the same I
2
C-bus:
• Up to 16 PCA85176 for very large LCD applications
• The use of two types of LCD multiplex drive modes
The I
2
C-bus protocol is shown in Figure 21. The sequence is initiated with a START
condition (S) from the I
2
C-bus master which is followed by one of the two possible
PCA85176 slave addresses available. All PCA85176 whose SA0 inputs correspond to
bit 0 of the slave address respond by asserting an acknowledge in parallel. This I
2
C-bus
transfer is ignored by all PCA85176 whose SA0 inputs are set to the alternative level.
Table 17. I
2
C slave address byte
Slave address
Bit 7 6 5 4 3 2 1 0
MSB LSB
011100SA0R/W
