PCA85176 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 6 — 7 April 2015 40 of 60
NXP Semiconductors
PCA85176
40 x 4 automotive LCD driver for low multiplex rates
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCA85176. Synchronization is guaranteed after a power-on reset. The only time that
SYNC
is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by defining a multiplex drive mode when PCA85176
with different SA0 levels are cascaded).
SYNC
is organized as an input/output pin. The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCA85176 asserts the SYNC
line at
the onset of its last active backplane signal and monitors the SYNC
line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCA85176 to assert
SYNC
. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCA85176 are shown in Figure 28
.
The PCA85176 can always be cascaded with other devices of the same type or
conditionally with other devices of the same family. This allows optimal drive selection for
a given number of pixels to display. Figure 25
and Figure 28 show the timing of the
synchronization signals.
Only one master but multiple slaves are allowed in a cascade. All devices in the cascade
have to use the same clock whether it is supplied externally or provided by the master.
(1) Is master (OSC connected to V
SS
).
(2) Is slave (OSC connected to V
DD
).
Fig 27. Cascaded PCA85176 configuration
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