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MTA18ASF1G72PF1Z-2G1T12AB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
Timing Parameters
Several system-level timing parameters are specific to the operation of the Micron
NVDIMM.
Table 7: Timing Parameters
Parameter/Condition Symbol
Diamond3 PowerGEM
Units NotesTypical Max
Micron NVDIMM controller I
2
C bus commands re-
sponse from a power-up condition
t
HW_RDY 2 3 sec
Micron NVDIMM controller charging ultracapacitors
t
GTG 8GB 245 550 sec 1
Micron NVDIMM controller copying DRAM contents
to NAND Flash
t
SAVE 8GB 50 60 sec
Micron NVDIMM controller copying an image from
NAND Flash to DRAM
t
RESTORE 8GB 40 60 sec 2
Point at which sufficient NAND is available for a
SAVE after a RELEASE NAND FLASH command is is-
sued
t
R_NF 2 4 sec
BACKUP trigger changing state to MUX. Host must
continue to maintain V
DD
, keep SDRAM in self re-
fresh, and not assert DDR4 RESET_n to avoid data
loss.
t
MUX_SWITCH – 50 μs
DRAM enters self refresh by CKE going LOW after
BACKUP trigger (either SAVE_n/230 or EXT PGEM
Trigger). If CKE is not asserted LOW within
t
CKE_LOW, the NVDIMM assumes the BACKUP trig-
ger was not intended and aborts the SAVE. The
BACKUP is still enabled for a future event.
t
CKE_LOW – 200 ms 3
Notes:
1. All conditions defined in the NVDIMM firmware specification must be met for GTG to
assert, indicating to the host that the NVDIMM can be used as nonvolatile memory.
t
GTG MAX will be dictated by the charge time of the ultracapacitors from a completely
discharged state. Values shown in this table reflect times observed with a typical Power-
GEM configuration for the given NVDIMM density. The actual maximum time will de-
pend on the specific PowerGEM used. See the PowerGEM data sheet for details.
2. Maximum restore time based on 10,000 ECC correction limit on the NAND Flash.
3. Only applies to BACKUP triggers that utilize CKE as a qualifier.
8GB (x72, ECC, SR) 288-Pin DDR4 Nonvolatile RDIMM
Timing Parameters
PDF: 09005aef85c5dc9c
asf18c1gx72pf1z.pdf - Rev. C 03/16 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device's data sheet is not implied. Exposure to ab-
solute maximum rating conditions for extended periods may adversely affect reliability.
Table 8: Absolute Maximum Ratings
Symbol Parameter Min Max Units Notes
V
DD
V
DD
supply voltage relative to V
SS
–0.4 1.5 V 1
V
DDQ
V
DDQ
supply voltage relative to V
SS
–0.4 1.5 V 1
V
PP
Voltage on V
PP
pin relative to V
SS
–0.4 3.0 V 2
12V Voltage on 12V pin relative to V
SS
–0.4 13.8 V
V
IN
, V
OUT
Voltage on any pin relative to V
SS
–0.4 1.5 V
Notes:
1. V
DDQ
balls on DRAM are tied to V
DD
.
2. V
PP
must be greater than or equal to V
DD
at all times.
Table 9: Operating Conditions
Symbol Parameter Min Nom Max Units Notes
V
DD
V
DD
supply voltage 1.14 1.2 1.26 V 1
V
PP
DRAM activating power supply 2.375 2.5 2.750 V 2
12V Auxiliary NVDIMM power supply 6 12 13.8 V
V
REFCA(DC)
Input reference voltage command/address bus 0.49 × V
DD
0.5 × V
DD
0.51 × V
DD
V 3
V
TT
Termination reference voltage (DC) – command/
address bus
0.49 × V
DD
-
20mV
0.5 × V
DD
0.51 × V
DD
+
20mV
V 4
I
I
Input leakage current; Any input excluding ZQ; 0V ≤
V
IN
≤ 1.1V
– – – µA 5
I
I
Input leakage current; ZQ –3 – +3 µA 6, 7
I
I/O
Output leakage current; 0V ≤ V
OUT
≤ V
DD
DQ, DQS_t,
DQS_c,
ALERT_n
–4 0 +4 µA 7
I
I/O
Output leakage current; V
OUT
= V
DD
; DQ and ODT
are disabled
– – 5 µA
I
I/O
Output leakage current; V
OUT
= V
SS
; DQ and ODT
are disabled with ODT input HIGH
– – 50 µA
I
VREFCA
V
REF
supply leakage current; V
REFDQ
= V
DD
/2 orV
REFCA
= V
DD
/2 (All other pins not under test = 0V)
–2 0 +2 µA 7
Notes:
1. V
DDQ
balls on DRAM are tied to V
DD
.
2. V
PP
must be greater than or equal to V
DD
at all times.
3. V
REFCA
must not be greater than 0.6 x V
DD
. When V
DD
is less than 500mV, V
REF
may be
less than or equal to 300mV.
4. V
TT
termination voltages in excess of specification limit will adversely affect command
and address signals' voltage margins, and reduce timing margins.
8GB (x72, ECC, SR) 288-Pin DDR4 Nonvolatile RDIMM
Electrical Specifications
PDF: 09005aef85c5dc9c
asf18c1gx72pf1z.pdf - Rev. C 03/16 EN
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
5. Command and address inputs are terminated to V
DD
/2 in the registering clock driver. In-
put current is dependent on terminating resistance selected in registering clock driver.
6. Tied to ground. Not connected to edge connector.
7. Multiply by number of DRAM die on module.
Table 10: Thermal Characteristics
Symbol Parameter/Condition Value Units Notes
T
C
Commercial operating case temperature 0 to 85 °C 1, 2, 3
>85 to 95 °C 1, 2, 3, 4
T
OPER
Normal operating temperature range 0 to +85 °C 5, 6
Extended temperature operating range (optional) >85 to 95 °C 5, 6
Notes:
1. Maximum operating case temperature. T
C
is measured in the center of the DRAM pack-
age.
2. A thermal solution must be designed to ensure the DRAM device does not exceed the
maximum T
C
during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T
C
dur-
ing operation.
4. If T
C
exceeds 85°C, the DRAM device must be refreshed externally at 2X refresh (a 3.9µs
interval refresh rate).
5. The refresh rate must double when 85°C < T
OPER
≤ 95°C.
6. For additional information, refer to technical note TN-00-08: "Thermal Applications,"
available on micron.com.
Table 11: LED Activity Table
LED State Function
D1 Green
Power
ON Power is present at NV controller.
OFF Power is not present at NV controller.
D2 Blue
Save/Restore
Fast blink
(On for 100 ms/
Off for 200 ms)
When a SAVE_n or a RESTORE operation is in progress.
Slow Blink
(every 15 seconds)
Normal operation: Controller fabric and FW has been loaded. NVDIMM is op-
erational from host perspective.
D3 Amber
User Defined
ON/OFF The state of this LED is user configurable. The host may write 0x01 to the LED
register (0x10) to turn the amber LED ON, and 0x00 to turn the amber LED
off. Reading this register returns the state of the output register, not the buf-
fered LED driver output.
Any Any Undefined NVDIMM hardware or firmware failure
Table 12: PowerGEM Proprietary Interface Connector (J3)
Pin Signal Name Signal Type Description
1 PGM_SCL Output SMB clock for PGEM slave unit.
2 PGM_SDA I/O SMB data for PGEM slave unit.
8GB (x72, ECC, SR) 288-Pin DDR4 Nonvolatile RDIMM
Electrical Specifications
PDF: 09005aef85c5dc9c
asf18c1gx72pf1z.pdf - Rev. C 03/16 EN
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
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MTA18ASF1G72PF1Z-2G1T12AB

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Manufacturer:
Micron
Description:
MODULE DDR4 NVDIMM 8GB NVRDIMM-N
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New from this manufacturer.
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