LTC4110
13
4110fb
and ranges. It should be noted that even if the LTC4110
TYPE pin is not set to a smart battery mode, any SMBus
commands sent by a host or a smart battery are still
acted upon. For SuperCap support, see the Applications
Information section.
BATTERY BACKUP MODE
Figure 1 shows the LTC4110 in backup mode and the
corresponding PowerPath enabled. The LTC4110 use the
DCDIV pin to typically monitor the DCIN voltage through
an external resistor divider. The DCDIV pin sets the backup
mode threshold voltage and senses the need to enter
backup mode. DCDIV can alternately be driven with other
signals such as logic. When the DCDIV pin voltage drops
below the AC present threshold voltage (see V
AC
) backup
mode is entered. Backup mode is also entered whenever
the internal undervoltage lockout, UVLO, senses that DCIN
(V
UVD
) or DCOUT has fallen to excessively low voltages.
In backup mode the battery P-MOSFET ideal diode is
enabled to backup the load from the battery. The supply
input P-MOSFET ideal diode isolates the main supply
input from the load and the fl yback switcher N-MOSFETs
are inhibited from turning on. Also, after the threshold is
passed, hysteresis (V
ACH
) is switched in. When the supply
is returning and the AC present threshold voltage plus the
hysteresis voltage is reached on the DCDIV pin, both of the
battery P-MOSFETs are rapidly switched off (t
dDOFF
) and
the supply input P-MOSFET ideal diode provides the load
current. When forward biased, the ideal diodes regulate
their forward voltage drop to 20mV typical (V
FR
) when the
MOSFET is suffi ciently sized. If the voltage input falls and
results in a forward voltage below 20mV, then the ideal
diode will begin turning off at a slow rate. Should the ideal
diode see a –18mV typical (V
REV
) or lower reverse voltage,
the ideal diode will turn off quickly (t
dDOFF
).
While in backup, the battery’s average cell voltage is moni-
tored to protect the battery from excessive discharge. If
the cell voltage drops below the value programmed by the
V
DIS
pin (Li-Ion default = 2.75V/cell, NiMH/NiCd default
= 0.95V/cell, lead acid default = 1.93V/cell), the battery
P-MOSFETs are rapidly turned off and the battery is dis-
connected from the load. If DCIN is above UVLO, the load
and the LTC4110 will be powered from the supply input. If
DCIN is below UVLO, the LTC4110 enters the micropower
shutdown mode (see the Shutdown Mode section for more
details). Also, the SMBus accessible BKUP_FLT fault bit
is set and maintained as long as suffi cient battery voltage
is present (V
BAT
≥ 2.7V). This fault bit can be read after
DCIN returns to a voltage level exceeding the internal
UVLO threshold (see V
UVI
) and DCOUT has regained suf-
fi cient voltage (see DCOUT) to provide internal power. If
the GPIO2 port is programmed as the BKUP_FLTb status
output after DCIN returns, it will be forced low to repre-
sent an inverted BKUP_FLT bit. When DCIN returns, as
sensed by the UVLO, the shutdown mode is automatically
cancelled and normal operation can resume, however, the
BKUP_FLT bit remains set until either the SHDN pin is set
high (all registers reset) or register bits POR_RESET or
BUFLT_RST are set. See the Shutdown Mode section for
details. During backup, the external thermistor network
is monitored for battery presence.
BATTERY CHARGE MODE
Figure 2 shows the charge path to charge a battery. Cur-
rent is pulled from the supply input to charge the battery.
At the same time, the input supply provides power to
both the system load and the backup load. The battery
is isolated from the load at all times so it cannot affect
charger terminations algorithms.
If we ignore battery chemistry for a moment, as far as the
LTC4110 charger is concerned, there are only two basic
charge modes. When the TYPE pin selects a standard bat-
tery mode, charge termination is controlled by the LTC4110
OPERATION
Figure 1. Backup Mode Operation
LTC4110
INID BATID
DCDIV
DCHFET
CHGFET
UVLO
SET POINT
BACKUP LOAD (DCOUT)
CURRENT FLOW
SYSTEM LOAD
BATTERY
DCIN
0V
ON ONOFF
4110 F01
