LTC4110
40
4110fb
If the TYPE pin is set for SLA/LEAD ACID or any nickel
based smart battery, the TIMER pin is not used. You can
ground the TIMER pin. Furthermore, if there is no need
of any timer function and there is no need of any voltage
divider from V
REF
to ground, you must still keep a load on
the V
REF
pin between 10µA and 25µA. It is recommended
you place a 49.9k load resistor from V
REF
to ground.
CHARGING BATTERIES OVER 12 HOURS
In situations where required bulk charge time cycle will
exceed the 12 hour time limit imposed by the charge TIMER
pin, you have two options. You can have an SMBus host
clear the CHG_FLT bit and force start another charge cycle
or you can switch to a smart version of the same battery.
If you chose the former, reduce the TIMER pin time to
about 2/3 of the actual time required. This will result in
faster termination in the second cycle and with autorestart
cycles when V
AR
is tripped. If you choose the smart bat-
tery option, the smart battery itself safely controls charge
termination. Bulk charge can last as long as necessary
to charge the battery to 100%. No host is required to do
anything, as the battery will maintain its full charge state
using its SMBus charge commands.
PROGRAMMING AC PRESENT INDICATION DELAY
TIME WITH ACPDLY AND V
REF
PINS
When the main supply, DCIN, returns after a power failure
the ACPb pin is driven low to indicate presence of main
power. This transition can be delayed to allow time for the
system to stabilize before actions are taken by the system
based on this pin status. The high to low transition only
delay on the ACPb pin can be programmed by selection
of capacitance on the ACPDLY pin, but is dependent upon
resistance on the V
REF
pin. Typical programmed delay times
range from 10ms to 200ms and is set as follows:
C
ACPDLY
(F) =
T(s)
2•R
VREF
(Ω)
As an example if R
VREF
= 113k and the desired delay time
is 105ms then C
TIMER
= 470nF. See t
AC
in the Electrical
Characteristics Table for the tolerance.
where
V
CUTOFF
= adjusted cutoff threshold voltage
V
CAL
/V
DIS
= voltage on V
CAL
or V
DIS
pin
V
BGR
=1.220V
The resistor divider connected to V
REF
pin will affect timer.
See the Programming Charge Time with TIMER and V
REF
Pins section for more details.
PROGRAMMING CHARGE TIME WITH TIMER AND
V
REF
PINS
Charge time limits for Li-Ion batteries can be programmed
by selection of capacitance on the TIMER pin, but is
dependent upon resistance on the V
REF
pin. Typical pro-
grammed bulk charge times range from 2 to 12 hours
and is set as follows:
C
TIMER
(F) =
T(Hrs)
(944 R
VREF
(Ω))
As an example if R
VREF
= 113k and the desired bulk charge
time limit is fi ve hours then C
TIMER
= 47nF. See F
TMR
which directly affects the 944 constant in the Electrical
Characteristics Table for the tolerance.
Avoid capacitors with high leakage currents. The V
REF
pin load resistor range is 49k to 125k or 10µA to 25µA of
load current. At 125k the maximum capacitance on V
REF
is limited to a maximum of 50pF to maintain suffi cient AC
stability for the internal amplifi er. At 49k the maximum is
125pF. The maximum capacitance is inversely proportional
to the resistance.
The voltage (V
REF
) on the V
REF
pin can be used as a
precision voltage for other uses with some limitations.
The total V
REF
pin current must not exceed 25µA and the
capacitance must be limited as discussed above. Load
current fl uctuations will modulate the programmed charge
time. In shutdown mode V
REF
will drop to 0V.
In some applications a divided down V
REF
voltage is needed
to program the SELA, SELC, TYPE, V
CHG
, V
CAL
and V
DIS
pins. This is easily implemented by use of a resistor divider
connected from V
REF
to GND that sets the V
REF
pin current
instead of a single resistor.
APPLICATIONS INFORMATION
LTC4110
41
4110fb
Avoid capacitors with high leakage currents. See the
Programming Charge Time with TIMER and V
REF
Pins
section for details concerning the V
REF
pin. For minimum
delay open the ACPDLY pin.
BAT PIN CURRENT IN IDLE MODE
When LTC4110 is in IDLE mode (i.e., not in charge, calibra-
tion or backup mode), there will be a typical 30µA current
pulled from the battery through the BAT pin, if this current
is of concern, a diode in series with a resistor can be con-
nected between DCIN and battery to compensate it.
SHOW BATTERY FULL WITH ACPB AND CHGB
Tie the source of an N-MOSFET to ACPb, gate to CHGb and
drain in series with R to an LED to show battery full. In
that case if CHG or ACP status LED is not needed, replace
it with a short but keep the pull-up resistor.
This current ramp starts at zero right after the primary side
MOSFET (CHGFET in charge mode, DCHFET in calibration
mode) is turned on. The current rises linearly towards a
peak of V
SEC
/400k (where V
SEC
= BAT in charge mode,
V
SEC
= DCIN in calibration mode), shutting off once the
primary side MOSFET is turned off. A series resistor (R
SL
)
connecting the I
SENSE
pin to the current sense resistor
(R
SNS(FET)
) thus develops a ramping voltage drop. From
the perspective of the I
SENSE
pin, this ramping voltage
adds to the voltage across the sense resistor, effectively
reducing the current comparator threshold in proportion
to duty cycle. This stabilizes the control loop against
subharmonic oscillation. The amount of reduction in the
current comparator threshold (ΔV
ISENSE
) can be calculated
using the following equation:
ΔV
ISENSE
= DUTY CYCLE
V
SEC
400k
•R
SL
To program m = m2,
R
N
kR
FLm
SL
SNSFET
=
1
400
,
where
N = transformer turns ratio N
BAT
/N
DCIN
R
SNS(FET)
= sense resistor connected between MOSFET
and GND
f = switching frequency
Lm = magnetizing inductance of the transformer
Designs not needing slope compensation may replace
R
SL
with a short.
CALCULATING IC POWER DISSIPATION
The power dissipation of the LTC4110 is dependent upon
the gate charge of the two MOSFETs (Q
G1
and Q
G2
). The
gate charge is determined from the manufacturers data
sheet and is dependent upon both the gate voltage swing
and the drain voltage swing of the MOSFET. Use 5V for
the gate voltage swing and V
DCIN
for the drain voltage
swing.
P
D
= V
DCIN
• (f
OSC
(Q
G1
+ Q
G2
) + I
Q
)
APPLICATIONS INFORMATION
Figure 18. Display Battery Full
FULL ACP
+5V
CHG
CHGb
ACPb
4110 F18
FLYBACK COMPENSATION
The values given for the I
TH
pin in the application schematics
have been found to compensate both the voltage loop and
current loop quite well. However, if the resistor connected
to I
CHG
, I
CAL
or I
PCC
is larger than 100k, a 37k resistor in
series with a 100nF capacitor should also be connected
between that pin and GND to compensate the loop.
SLOPE COMPENSATION
The LTC4110 injects a ramping current through its I
SENSE
pin into an external slope compensation resistor (R
SL
).
LTC4110
42
4110fb
Example:
V
DCIN
= 12V, f
OSC
= 300kHz, Q
G1
= Q
G2
= 15nC,
I
Q
= 3mA
P
D
= 144mW
SNUBBER DESIGN
The values given in the applications schematics have been
found to work quite well for this 12V-1A application. Care
should be taken in selecting other values for your applica-
tion since effi ciency may be impacted by a poor choice.
For a detailed look at snubber design, Application Note
19 is very helpful.
COMPONENT SELECTION
Current Sense Resistors
The LTC4110 uses up to three sense resistors—one of
them optional. In general, current sense resistors should
have a low temperature coeffi cient and suffi cient power
dissipation capability to avoid self-heating. Tolerance
depends on system accuracy requirements.
R
SNS(FET)
:
The power rating of R
SNS(FET)
is defi ned by the
highest value between I
CHG
or I
CAL
and the transformer
turns ratio. Use one the following equations to calculate
I
RSNS(FET)
depending on which value, I
CHG
or I
CAL
which-
ever is higher.
I
R(SNSFETCHG)
=
I
CHG
1+
V
BAT
N V
DCIN
N V
BAT
E
2
V
DCIN
+ 1
I
R(SNSFETCAL)
=
I
CAL
1+
V
BAT
N V
DCIN
NE
2
V
BAT
V
DCIN
+ 1
Plug in the higher value of the above two results as
I
R(SNSFET)
and solve for power:
P
R(SNSFET)
= I
R(SNSFET)
2
R
SNS(FET)
R
CL
:
R
CL
power rating is a function of the maximum forward
current the system load draws. See Figure 11.
P
R(CL)
= I
MAX
2
R
CL
Find a sense resistor who’s power rating is greater than
P
R(CL)
R
SNS(BAT)
:
R
SNS(BAT)
power rating is a function of the
highest current value between I
CHG
or I
CAL
with which
the battery will work. Plug in the higher of the two into
I
BAT(MAX)
and solve:
P
R(SNSBAT)
= I
MAX
2
R
SNS(BAT)
Use a sense resistor with a power rating greater than
P
SNS(BAT)
FLYBACK MOSFET SELECTION
The LTC4110 uses two low side N-channel switching
MOSFETs in its fl yback converter. These MOSFETs have
dual roles. An any given time, only one MOSFET is the
primary switch while the other acts as a synchronous recti-
er on the secondary to improve effi ciency. The individual
MOSFETs’ roles depend on whether the battery is being
charged or calibrated. Each MOSFET specifi cation must
account for both roles.
The MOSFET voltage ratings in a fl yback design must deal
with other factors beyond
V
IN
. During switch “on” time, a
current is established in the primary leakage inductance
(L
L
) equal to peak primary current (I
PRI
). When the switch
turns off, the energy stored in L
L
, (Energy = I
PRI
2
L
L
/2)
causes the switch voltage to fl y up, starting from the input
voltage on up to the breakdown of the MOSFET if the volt-
age is not clamped. Thus, the snubber design is critical
in dealing with this voltage spike and can infl uence the
MOSFET voltage selection value. From a MOSFET point
of view, the minimum voltage must be greater than the
snubber clamp voltage V
SNUB
. If V
SNUB
itself is too low,
zener clamp dissipation rises rapidly thus encouraging
higher MOSFET voltages.
The maximum DC voltage that
the N-channel MOSFETs sees is:
VV
V
N
CHG FET DCIN
BAT
()
=+
VVNV
CAL FET BAT DCIN()
=+
APPLICATIONS INFORMATION

LTC4110EUHF#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Bat Backup S Manager
Lifecycle:
New from this manufacturer.
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