LTC4110
28
4110fb
OPERATION
processed to allow compliance with smart battery charge
and discharge termination and protection control. How-
ever, there is no actual value processing of the voltage or
current charge commands. IC will acknowledge all smart
battery write commands, but process only a subset of
them. Full SMBus error and reset handling is supported.
The SMBus remains functional during backup mode, but
not in SHDN mode.
The LTC4110 SMBus address can be changed when
standard batteries are used to facilitate redundant backup
systems. Connect SELA pin to GND for 12h, V
DD
for 28h
and V
REF
for 20h. When a smart battery is selected by the
TYPE pin the SELA pin must be connected to GND to select
address 12h. Note: Although there are only 7 address bits
for SMBus, the above addresses shown follow the smart
battery convention of including the Read/Write bit as part
of the address value. The Read/Write bit becomes the
LSB of the SMBus address with the Read/Write bit value
assumed to be a 0 value.
If multiple LTC4110s with smart batteries are to be used,
each LTC4110 must be SMBus isolated from all other
LTC4110s so the main bus or host bus can only see one
LTC4110 and its corresponding smart battery at a time.
Failure to do so will cause multiple LTC4110s and smart
batteries responding to a single host query resulting in
errors. There are multiple channel SMBus multiplexer ICs
such as the LTC4305 and LTC4306 to help implement the
required isolation. Furthermore, if a given SMBus is high
in SMBus device count or long in length, you may want to
consider using SMBus accelerators. The above ICs listed
support that option.
If the SMBus is not used or to force all GPIOs to status
mode upon power-up, connect SELA to a typically 0.5 •
V
REF
voltage from V
REF
pin resistor divider. The SMBus
address then, if used, will be 12h.
Pull-ups are required on the SDA and SCL pin such that
when they are not being used, they are in a default high
state that means no bus activity. The pull-up voltage need
only be high enough to satisfy the logic high threshold.
Tying the pins low is a valid state on the SMBus that
means anything but the bus is free. This state will force
the LTC4110’s internal SMBus state machine to reset itself
because it thinks the SMBus is hung.
The LTC4110 does not support or respond to the following
SMBus V1.1 timing specifi cations:
a) T
TIMEOUT
(This is not to be confused with the
LTC4110’s t
TIMEOUT
specifi cation.)
b) T
LOW:SEXT
c) T
LOW:MEXT
The above specifi cations have to do with detecting bus
hangs or SMBus devices that are taking too long to reply
using clock stretching and slowing down the SMBus
bandwidth. The LTC4110 is a slave only device that does
not do any clock stretching and works all the way up to
maximum 100kHz bus speed. It will not hang the bus.
The design will always reset its SMBus interface upon
receiving an SMBus Start Bit or a Stop Bit regardless of
the prior state of the bus.
