LTC4110
49
4110fb
TYPICAL APPLICATIONS
Battery Backup System Manager Controlling a Nine-Series Cell NiMH Battery with
Calibration Managed by Host Processor
DCIN
INID
CLN
CLP
DCDIV
THA
V
REF
10k
NTC
I
2
C
TO
HOST
0.1µF
LOW
ESR
20µF
VERY
LOW ESR
BATTERY
IDEAL
DIODE
INPUT
IDEAL DIODE
TO SYSTEM
LOAD
TO BACKUP
LOAD
V
CHG
V
CAL
V
DIS
I
CHG
I
CAL
I
PCC
SELA
SELC
SDA
SCL
TYPE
DCOUT
SUPPLY
INPUT
(12V)
NC
BATID
CHGFET
DCHFET
I
SENSE
CSP
CSN
BAT
I
TH
ACPDLY
TIMER
V
DD
ACPb
GP101
GP102
GP103
SHDN
GND SGND
20µF
VERY
LOW ESR
+
+
+
+
+
+
+
+
+
I
2
C
TO
HOST
4110 TA05
LTC4110
0.1µF
LOW
ESR
0.1µF
LOW
ESR
THB
R
THA
1.13k
R
THB
54.9k
1.21k
49.9k
8.66k
R
SNS(FET)
0.05
0.5W
33
0.5W
5%
33
0.5W
5%
R
SL
3.32k
R
CL
0.02
1W
3.01k
0.1µF
0.1µF
1k2k
330nF
1nF1nF
1k2k
330nF
R
SNS(BAT)
0.1
0.25W
NO TIMER
HIGH CURRENT BACKUP LOAD DESIGN
0.5A BACKDRIVE CURRENT CUTOFF (CALIBRATION)
1A CHARGE AND CALIBRATION CURRENT
0.2A WAKE-UP/PRECONDITIONING CURRENT
HOST PROVIDES SMBus PULL-UP RESISTORS
ALL RESISTORS ARE 1% UNLESS NOTED OTHERWISE
Q1: Si7216DN
Q2: Si7445DN
Q3: Si7983DP
T1: BH510-1019
Q2
Q3
Q1A
Q1B
36.5k
187k
37.4k
10.8V (9 CELL)
T1
LTC4110
50
4110fb
TYPICAL APPLICATIONS
Dual Battery Backup System Managers Controlling a Two Three-Series Cell Li-Ion, Gas Gauge Smart
Batteries with Calibration Managed by Host Processor and SMBus Multiplexer
DCIN
INID
CLN
CLP
DCDIV
THA
V
REF
10k
NTC
SMB2
SMB1
SMB2
SMB1
0.1µF
LOW
ESR
20µF
VERY
LOW ESR
BATTERY
IDEAL
DIODE
INPUT
IDEAL DIODE
TO BACKUP
LOAD
SELC
SDA
SCL
TYPE
DCOUT
NC
BATID
CHGFET
DCHFET
I
SENSE
CSP
CSN
BAT
I
TH
ACPDLY
TIMER
V
DD
ACPb
GP101
GP102
GP103
SHDN
GND SGND
20µF
VERY
LOW ESR
+
+
+
SMB2
4110 TA06
LTC4110
0.1µF
LOW
ESR
0.1µF
LOW
ESR
THB
R
THA
1.13k
R
THB
54.9k
DCIN
INID
CLN
CLP
DCDIV
THA
V
REF
10k
NTC
BATTERY 2 (12.6V)
10.8V
3 CELL
10.8V
3 CELL
BATTERY 1 (12.6V)
0.1µF
LOW
ESR
20µF
VERY
LOW ESR
BATTERY
IDEAL
DIODE
INPUT
IDEAL DIODE
TO SYSTEM
LOAD
SELC
SDA
SCL
TYPE
DCOUT
SUPPLY
INPUT
(12V)
NC
BATID
CHGFET
DCHFET
I
SENSE
CSP
CSN
BAT
I
TH
ACPDLY
TIMER
V
DD
ACPb
GP101
GP102
GP103
SHDN
GND SGND
20µF
VERY
LOW ESR
+
+
+
SMB1
SMBUS
MULTIPLEXOR
HOST
I
2
C/SMBus
LTC4305
LTC4110
0.1µF
LOW
ESR
0.1µF
LOW
ESR
THB
R
THA
1.13k
R
THB
54.9k
V
CHG
V
CAL
V
DIS
I
CHG
I
CAL
I
PCC
SELA
1.21k
113k
8.66k
R
CL
0.02
1W
0.1µF
7HR CHARGE TIME
HIGH CURRENT BACKUP LOAD DESIGN
0.5A BACKDRIVE CURRENT CUTOFF
1A CHARGE AND CALIBRATION CURRENT
0.2A WAKE-UP/PRECONDITIONING CURRENT
ALL RESISTORS ARE 1% UNLESS NOTED OTHERWISE
SEE LTC4305 DATA SHEET FOR PULL-UP INFORMATION
Q1, Q2: Si7216DN
Q3, Q4: Si7445DP
Q5, Q6: Si7983DP
T1, T2: BH510-1019
Q3
37.4k
36.5k
187k
V
CHG
V
CAL
V
DIS
I
CHG
I
CAL
I
PCC
SELA
113k
0.1µF
37.4k
36.5k
187k
R
SNS(FET)
0.05
0.5W
33
0.5W
5%
33
0.5W
5%
R
SL
3.32k
3.01k
0.1µF
68nF
1k2k
330nF
1nF1nF
1k2k
330nF
R
SNS(BAT)
0.1
0.25W
Q5
Q1A
Q1B
R
SL
3.32k
3.01k
0.1µF
1k2k
330nF
1k2k
330nF
Q6
R
SNS(FET)
0.05
0.5W
33
0.5W
5%
33
0.5W
5%
R
SL
3.32k
3.01k
0.1µF
68nF
1k2k
330nF
1nF1nF
1k2k
330nF
R
SNS(BAT)
0.1
0.25W
Q2A
Q2B
Q4
T2T1
LTC4110
51
4110fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701)
5.00 p 0.10
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.50 REF
5.15 ± 0.10
7.00 p 0.10
0.75 p 0.05
R = 0.125
TYP
R = 0.10
TYP
0.25 p 0.05
(UH) QFN REF C 1107
0.50 BSC
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 REF
3.15 ± 0.10
0.40 p0.10
0.70 p 0.05
0.50 BSC
5.5 REF
3.00 REF
3.15 ± 0.05
4.10 p 0.05
5.50 p 0.05
5.15 ± 0.05
6.10 p 0.05
7.50 p 0.05
0.25 p 0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45o CHAMFER

LTC4110EUHF#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Bat Backup S Manager
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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