OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LT1977EFE#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LT1977
19
1977fa
APPLICATIO S I FOR ATIO
WUUU
the user to generate a delayed signal after the power good
threshold is exceeded.
Referring to Figure 2, the PGFB pin is the positive input to
a comparator whose negative input is set at V
PGFB
. When
PGFB is taken above V
PGFB
, current (I
CSS
) is sourced into
the C
T
pin starting the delay period. When the voltage on
the PGFB pin drops below V
PGFB
the C
T
pin is rapidly
discharged resetting the delay period. The PGFB voltage is
typically generated by a resistive divider from the regu-
lated output or input supply.
The capacitor on the C
T
pin determines the amount of
delay time between the PGFB pin exceeding its threshold
(V
PGFB
) and the PG pin set to a high impedance state.
When the PGFB pin rises above V
PGFB
current is sourced
(I
CT
) from the C
T
pin into the external capacitor. When the
voltage on the external capacitor reaches an internal clamp
(V
CT
), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = C
CT
•(V
CT
)/(I
CT
). If
the voltage on the PGFB pin drops below its V
PGFB
, C
CT
will
be discharged rapidly and PG will be active low with a
200µA sink capability. If the SHDN pin is taken below its
threshold during normal operation, the C
T
pin will be
discharged and PG inactive, resulting in a non Power Good
cycle when SHDN is taken above its threshold. Figure 9
shows the power good operation with PGFB connected to
FB and the capacitance on C
T
= 0.1µF. The PGOOD pin has
Figure 9. Power Good
V
OUT
500mV/DIV
PG
100k TO V
IN
V
CT
500mV/DIV
V
SHDN
2V/DIV
TIME (10ms/DIV)
1977 F09
V
IN
PG
PGFB
LT1977
PG at 80% V
OUT
with 100ms Delay
0.27µF
C
OUT
C
OUT
200k
V
OUT
= 3.3V
153k
12k
100k
FB
C
T
V
IN
PG
PGFB
LT1977
V
OUT
Disconnect at 80% V
OUT
with 100ms Delay
0.27µF
200k
V
OUT
= 3.3V
153k
12k
100k
FB
C
T
V
IN
PG
PGFB
LT1977
PG at V
IN
> 4V with 100ms Delay
0.27µF
V
OUT
= 3.3V
200k
511k
200k
100k
165k
FB
C
T
V
IN
PG
PGFB
LT1977
V
OUT
Disconnect 3.3V Logic Signal
with 100µs Delay
270pF
200k
V
OUT
= 12V
1977 F10
866k
100k
FB
C
T
C
OUT
C
OUT
Figure 10. Power Good Circuits
LT1977
20
1977fa
APPLICATIO S I FOR ATIO
WUUU
a limited amount of drive capability and is susceptible to
noise during start-up and Burst Mode operation. If erratic
operation occurs during these conditions a small filter
capacitor from the PGOOD pin to ground will ensure
proper operation. Figure 10 shows several different con-
figurations for the LT1977 Power Good circuitry.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path, shown
in Figure 11, must be kept as short as possible. This is
Figure 12. Suggested Layout
Figure 11. High Speed Switching Path
NC
R2
C2
C5
R1
R3
C4
SW
NC
V
IN
NC
BOOST
TCAP
GND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
PGOOD
SHDN
SYNC
PGFB
FB
V
C
BIAS
C
SS
1977 F12
C3
GND
GND
D1
L1
V
OUT
C1
C2 D2
MINIMIZE
D1-C3
LOOP
V
IN
KELVIN SENSE
FEEDBACK
TRACE AND
KEEP SEPARATE
FROM BIAS TRACE
CONNECT PIN 8 GND TO THE
PIN 17 EXPOSED PAD GND
PLACE VIA's UNDER EXPOSED
PAD TO A BOTTOM PLANE TO
ENHANCE THERMAL
CONDUCTIVITY
LT1977
C2 C1
1977 F11
D1
L1
V
IN
LT1977
V
OUT
V
IN
SW
42
HIGH
FREQUENCY
CIRCULATION
PATH
+
LOAD
implemented in the suggested layout of Figure 12. Short-
ening this path will also reduce the parasitic trace induc-
tance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a flyback spike across the
LT1977 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT1977 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The V
C
and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1977
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
Board layout also has a significant effect on thermal
resistance. Pin 8 and the exposed die pad, Pin 17, are a
continuous copper plate that runs under the LT1977 die.
This is the best thermal path for heat out of the package.
Reducing the thermal resistance from Pin 8 and exposed
pad onto the board will reduce die temperature and in-
crease the power capability of the LT1977. This is achieved
by providing as much copper area as possible around the
exposed pad. Adding multiple solder filled feedthroughs
under and around this pad to an internal ground plane will
also help. Similar treatment to the catch diode and coil
terminations will reduce any additional heating effects.
THERMAL CALCULATIONS
Power dissipation in the LT1977 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
P
RI V
V
tIVf
SW
SW OUT OUT
IN
EFF OUT IN
=
()( )
+
()
()()()
2
12/
LT1977
21
1977fa
APPLICATIO S I FOR ATIO
WUUU
Boost current loss:
P
VI
V
BOOST
OUT OUT
IN
=
()
()
2
32/
Quiescent current loss:
P
Q
= V
IN
(0.0015) + V
OUT
(0.003)
R
SW
= switch resistance (≈0.3 when hot )
t
EFF
= effective switch current/voltage overlap time
(t
r
+ t
f
+ t
IR
+ t
IF
)
t
r
= (V
IN
/1.1)ns
t
f
= (V
IN
/1.8)ns
t
IR
= t
IF
= (I
OUT
/0.05)ns
f = switch frequency
Example: with V
IN
= 12V, V
OUT
= 5V and I
OUT
= 1A:
Pee
TBD W
PW
PW
SW
BOOST
Q
=
()()()
+
()
()
()( )( )
+= + =
=
()
()
=
=
()
+
()
=
−
03 1 5
12
57 6 1 2 1 12 500 3
0 04 0 125 0 172 0 297
5132
12
0 002
12 0 0015 5 0 003 0 033
2
9
2
.
./
....
/
.
...
Total power dissipation is:
P
TOT
= 0.297 + 0.065 + 0.033 = 0.40W
Thermal resistance for the LT1977 package is influenced
by the presence of internal or backside planes. With a full
plane under the FE16 package, thermal resistance will be
about 45°C/W. No plane will increase resistance to about
150°C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:
T
J
= T
A
+ Q
JA
(P
TOT
)
With the FE16 package (Q
JA
= 45°C/W) at an ambient
temperature of 70°C:
T
J
= 70 + 45(0.40) = 98°C
Input Voltage vs Operating Frequency Considerations
The absolute maximum input supply voltage for the LT1977
is specified at 60V. This is based solely on internal semi-
conductor junction breakdown effects. Due to internal
power dissipation the actual maximum V
IN
achievable in a
particular application may be less than this.
A detailed theoretical basis for estimating internal power
loss is given in the section Thermal Considerations. Note
that AC switching loss is proportional to both operating
frequency and output current. The majority of AC switch-
ing loss is also proportional to the square of input voltage.
For example, while the combination of V
IN
= 40V, V
OUT
=
5V at 1A and f
OSC
= 500kHz may be easily achievable, si-
multaneously raising V
IN
to 60V and f
OSC
to 700kHz is not
possible. Nevertheless, input voltage transients up to 60V
can usually be accommodated, assuming the resulting
increase in internal dissipation is of insufficient time dura-
tion to raise die temperature significantly.
A second consideration is control. A potential limitation
occurs with a high step-down ratio of V
IN
to V
OUT
, as this
requires a correspondingly narrow minimum switch on
time. An approximate expression for this (assuming con-
tinuous mode operation) is given as follows:
t
ON(MIN)
= V
OUT
+ V
F
/V
IN
(f
OSC
)
where:
V
IN
= input voltage
V
OUT
= output voltage
V
F
= Schottky diode forward drop
f
OSC
= switching frequency
A potential control problem arises if the LT1977 is called
upon to produce an on time shorter than it is able to
produce. Feedback loop action will lower then reduce the
V
C
control voltage to the point where some sort of cycle-
skipping or Burst Mode behavior is exhibited.
In summary:
1. Be aware that the simultaneous requirements of high
V
IN
, high I
OUT
and high f
OSC
may not be achievable in
practice due to internal dissipation. The Thermal Con-
siderations section offers a basis to estimate internal
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

LT1977EFE#TRPBF

Mfr. #:
Buy LT1977EFE#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1.5A, 500kHz HV Step-down w/ Burst Mode Operation
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet