LT1977
4
1977fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
FB Voltage Oscillator Frequency SHDN Threshold
SHDN Pin Current
Shutdown Supply Current Sleep Mode Supply Current
Bias Sleep Current
1.20
VOLTAGE (V)
1.21
1.23
1.24
1.25
1.30
1.27
1.22
1.28
1.29
1.26
TEMPERATURE (°C)
–50 0
50
75
1977 G01
–25
25
100
125
TEMPERATURE (°C)
–50
450
FREQUENCY (kHz)
460
480
490
500
550
520
0
50
75
1977 G02
470
530
540
510
–25
25
100
125
VOLTAGE (V)
1.35
1977 G03
1.20
1.10
1.05
1.00
1.40
1.30
1.25
0.15
TEMPERATURE (°C)
–50 0
50
75
–25
25
100
125
SHDN VOLTAGE (V)
0
0
CURRENT (µA)
1.5
2.5
3.5
10
20
30 40
1977 G04
50
4.5
5.5
1.0
2.0
3.0
4.0
5.0
60
T
J
= 25°C
CURRENT (µA)
1977 G05
20
10
5
0
25
15
TEMPERATURE (°C)
–50 0
50
75
–25
25
100
125
V
IN
= 60V
V
IN
= 42V V
IN
= 12V
CURRENT (µA)
1977 G06
160
80
40
0
200
120
140
60
20
180
100
V
BIAS
= 0V
V
BIAS
= 5V
TEMPERATURE (°C)
–50 0
50
75
–25
25
100
125
CURRENT (µA)
1977 G07
160
80
40
0
200
120
140
60
20
180
100
TEMPERATURE (°C)
–50 0
50
75
–25
25
100
125
PGFB Threshold
VOLTAGE (V)
1977 G08
1.16
1.08
1.04
1.00
1.20
1.12
1.14
1.06
1.02
1.18
1.10
TEMPERATURE (°C)
–50 0
50
75
–25
25
100
125
PG Sink Current
CURRENT (µA)
1977 G09
200
100
50
0
250
150
TEMPERATURE (°C)
–50 0
50
75
–25
25
100
125
LT1977
5
1977fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Switch Peak Current Limit
Soft-Start Current Threshold
vs FB Voltage
Frequency Foldback Percentage
TEMPERATURE (°C)
–50
1.5
PEAK SWITCH CURRENT (A)
2.0
2.5
3.0
3.5
–25 0 25 50
1977 G10
75 100 125
FB VOLTAGE (V)
0
0
CURRENT (µA)
10
20
30
0.2
0.4
0.6 0.8
1977 G11
1.0
40
50
5
15
25
35
45
1.2
SOFT-START
DEFEATED
T
J
= 25°C
FB PIN VOLTAGE (V)
0
FOLDBACK PERCENTAGE (%)
60
80
100
1
1977 G12
40
20
50
70
90
30
10
0
0.25
0.5
0.75
1.25
Switch On Voltage (V
CESAT
)
LOAD CURRENT (A)
–0.1
0
VOLTAGE (mV)
50
150
200
250
500
350
0.3
0.7
0.9
1977 G13
100
400
450
300
0.1 0.5
1.1
1.3
1.5
T
J
= 125°C
T
J
= 25°C
T
J
= –50°C
INPUT VOLTAGE (V)
0
0
SUPPLY CURRENT (µA)
50
100
10
20
30 40
1977 F05
50
150
25
75
125
60
V
OUT
= 3.3V
T
A
= 25°C
Supply Current vs Input Voltage Minimum Input Voltage
Burst Mode Threshold
vs Input Voltage
INPUT VOLTAGE (V)
5
LOAD CURRENT (mA)
300
400
500
13
1977 G20
200
100
250
350
450
150
50
0
7
9
11
15
614
8
10
12
16 17 18 19
20
Burst Mode EXIT
(INCREASING LOAD)
Burst Mode ENTER
(DECREASING LOAD)
V
OUT
= 3.3V
L = 10µH
C
OUT
= 100µF
Minimum On Time Boost Current vs Switch Current
TEMPERATURE (°C)
–50
0
ON TIME (ns)
50
150
200
250
500
350
0
50
75
1977 G21
100
400
450
300
–25
25
100
125
LOAD CURRENT = 0.5A
LOAD CURRENT = 1A
SWITCH CURRENT (A)
0
0
BOOST CURRENT (mA)
5
15
20
25
1
45
1977 G22
10
0.5
0.25
1.25
0.75 1.5
30
35
40
LOAD CURRENT (A)
0
INPUT VOLTAGE (V)
5.0
5.5
6.0
1.6
1977 G19
4.5
4.0
3.0
0.40.2 0.8 10.6 1.2 1.4
3.5
7.5
6.5
7.0
5V START
5V RUNNING
3.3V START
3.3V RUNNING
LT1977
6
1977fa
UU
U
PI FU CTIO S
NC (Pins 1, 3, 5): No Connection.
SW (Pin 2): The SW pin is the emitter of the on-chip power
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the SW pin
negative during switch off time. Negative voltage is clamped
with the external catch diode. Maximum negative switch
voltage allowed is –0.8V.
V
IN
(Pin 4): This is the collector of the on-chip power NPN
switch. V
IN
powers the internal control circuitry when a
voltage on the BIAS pin is not present. High di/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the V
IN
pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the V
CE
voltage across the internal NPN.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.2 FET
structure.
C
T
(Pin 7): A capacitor on the C
T
pin determines the amount
of delay time between the PGFB pin exceeding its thresh-
old (V
PGFB
) and the PG pin set to a high impedance state.
When the PGFB pin rises above V
PGFB
, current is sourced
from the C
T
pin into the external capacitor. When the volt-
age on the external capacitor reaches an internal clamp
(V
CT
), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = C
CT
• V
CT
/I
CT
. If the
TYPICAL PERFOR A CE CHARACTERISTICS
UW
No Load 1A Step Response
Step Response
Burst Mode Operation
Burst Mode Operation
V
OUT
20mV/DIV
I
SW
500mA/DIV
V
IN
= 12V
V
OUT
= 3.3V
I
Q
= 100µA
2µs/DIV
1977 G15
V
OUT
50mV/DIV
I
OUT
500mA/DIV
V
IN
= 12V
V
OUT
= 3.3V
C
OUT
= 100µF
I
DC
= 0mA
500µs/DIV
1977 G17
V
OUT
50mV/DIV
I
OUT
500mA/DIV
V
IN
= 12V
V
OUT
= 3.3V
C
OUT
= 100µF
I
DC
= 350mA
500µs/DIV
1977 G18
V
OUT
20mV/DIV
I
SW
500mA/DIV
V
IN
= 12V
V
OUT
= 3.3V
I
Q
= 100µA
5ms/DIV
1977 G14
INPUT VOLTAGE (V)
2
OUTPUT VOLTAGE (V)
1.5
2.0
2.5
3.5
4.5
1977 G23
1.0
0.5
0
2.5 3 4
3.0
3.5
4.0
V
OUT
= 3.3V
BOOST DIODE = DIODES INC B1100
LOAD CURRENT = 250mA
LOAD CURRENT = 1.25A
Dropout Operation Dropout Operation
INPUT VOLTAGE (V)
2
0
OUTPUT VOLTAGE (V)
1
3
4
5
3
4
4.5 6.5
1977 G24
2
2.5 3.5
5
5.5
6
6
V
OUT
= 5V
BOOST DIODE = DIODES INC B1100
LOAD CURRENT = 250mA
LOAD CURRENT = 1.25mA

LT1977EFE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1.5A, 500kHz HV Step-down w/ Burst Mode Operation
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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