LT1977
22
1977fa
APPLICATIO S I FOR ATIO
WUUU
power. In questionable cases a prototype supply should
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high V
IN
, low V
OUT
and
high f
OSC
can result in an unacceptably short minimum
switch on time. Cycle skipping and/or Burst Mode be-
havior will result causing an increase in output voltage
ripple while maintaining the correct output voltage.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits. Read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/or
catch diode and connecting the V
C
compensation to a
ground track carrying significant switch current. In addi-
tion the theoretical analysis considers only first order non-
ideal component behavior. For these reasons, it is important
that a final stability check is made with production layout
and components.
The LT1977 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 12.
The LT1977 can be considered as two g
m
blocks, the error
amplifier and the power stage.
Figure 13 shows the overall loop response with a 330pF V
C
capacitor and a typical 100µF tantalum output capacitor.
Ω
The response is set by the following terms:
Error amplifier: DC gain is set by g
m
and R
O
:
EA Gain = 650µ • 1.5M = 975
Ω
The pole set by C
F
and R
L
:
EA Pole = 1/(2π • 1.5M • 330pF) = 322Hz
Unity gain frequency is set by C
F
and g
m
:
EA Unity Gain Frequency = 650µ /(2π • 330pF)
= 313kHz
Powerstage: DC gain is set by g
m
and R
L
(assume 10Ω):
PS DC Gain = 3 • 10 = 30
Pole set by C
OUT
and R
L
:
PS Pole = 1/(2π • 100µF • 10) = 159Hz
Unity gain set by C
OUT
and g
m
:
PS Unity Gain Freq = 3/(2π • 100µF) = 4.7kHz.
Tantalum output capacitor zero is set by C
OUT
and C
OUT
ESR
Output Capacitor Zero = 1/(2π • 100µF • 0.1) = 159kHz
The zero produced by the ESR of the tantalum output ca-
pacitor is very useful in maintaining stability. If better
transient response is required, a zero can be added to the
loop using a resistor (R
C
) in series with a compensation
capacitor(s). As the value of R
C
is increased, transient re-
sponse will generally improve but two effects limit its value.
Figure 14. Overall Loop Response
FREQUENCY (Hz)
0
PHASE (DEG)
90
45
135
100
–50
GAIN (dB)
0
50
100
100 1k 10k 100k
1977 F14
1M10
V
OUT
= 3.3V
C
OUT
= 100µF, 0.1Ω
C
F
= 330pF
R
C
/C
C
= NC
I
LOAD
= 350mA
Figure 13. Model for Loop Response
–
+
CURRENT MODE
POWER STAGE
g
m
= 3
Ω
g
m
= 650µ
Ω
1.25V
V
C
LT1977
ERROR
AMP
1.5MR
C
R1
FB
12
11
SW
2
ESR
OUTPUT
R2
C
OUT
1977 F13
C
FB
C
F
C
C
