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PCF8578T/1,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
2003 Apr 14 13
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
Fig.8 LCD drive mode waveforms for 1 : 16 multiplex rate.
MSA836
V
DD
V
2
V
V
V
V
3
4
5
LCD
T
frame
ROW 1
R1 (t)
V
DD
V
2
V
V
V
V
3
4
5
LCD
ROW 2
R2 (t)
V
DD
V
2
V
V
V
V
3
4
5
LCD
COL 1
C1 (t)
V
DD
V
2
V
V
V
V
3
4
5
LCD
COL 2
C2 (t)
dot matrix
1:16 multiplex rate
state 1 (OFF)
state 2 (ON)
0.2 V
op
0.2 V
op
0 V
V
op
V
op
V
state 1
(t)
0.2 V
op
0.2 V
op
0 V
V
op
V
op
V
state 2
(t)
0.6 V
op
0.6 V
op
V
state 1
(t) = C1(t) R1(t):
V
on(rms)
V
op
=
1
16
16 1
16 1
()
16
=
0.316
V
state 2
(t) = C2(t) R2(t):
V
off(rms)
V
op
=
16 1
16 1
()
16
=
0.254
2
2
()
general relationship (n = multiplex rate)
V
on(rms)
V
op
=
1
n
n
1
n
1
()
n
V
off(rms)
V
op
=
n
1
n
1
()
n
2
2
()
2003 Apr 14 14
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
7.5 Internal clock
The clock signal for the system may be generated by the
internal oscillator and prescaler. The frequency is
determined by the value of the resistor R
OSC
, see Fig.9.
For normal use a value of 330 kΩ is recommended.
The clock signal, for cascaded PCF8579s, is output at
CLK and has a frequency
1
⁄
6
(multiplex rate 1 : 8, 1 : 16
and 1 : 32) or
1
⁄
8
(multiplex rate 1 : 24) of the oscillator
frequency.
Fig.9 Oscillator frequency as a function of
external oscillator resistor, R
OSC
.
To avoid capacitive coupling, which could adversely affect oscillator
stability, R
OSC
should be placed as closely as possible to the OSC
pin. If this proves to be a problem, a filtering capacitor may be
connected in parallel to R
OSC
.
10
MSA837
10
2
10
3
10
4
1
10
3
10
10
2
f
OSC
(kHz)
R(kΩ)
OSC
7.6 External clock
If an external clock is used, OSC must be connected to
V
DD
and the external clock signal to CLK. Table 4
summarizes the nominal CLK and SYNC frequencies.
7.7 Timing generator
The timing generator of the PCF8578 organizes the
internal data flow of the device and generates the LCD
frame synchronization pulse SYNC, whose period is an
integer multiple of the clock period. In cascaded
applications, this signal maintains the correct timing
relationship between the PCF8578 and PCF8579s in the
system.
7.8 Row/column drivers
Outputs R0 to R7 and C32 to C39 are fixed as row and
column drivers respectively. The remaining 24 outputs
R8/C8 to R31/C31 are programmable and may be
configured (in blocks of 8) to be either row or column
drivers. The row select signal is produced sequentially at
each output from R0 up to the number defined by the
multiplex rate (see Table 1). In mixed mode the remaining
outputs are configured as columns. In row mode all
programmable outputs (R8/C8 to R31/C31) are defined as
row drivers and the outputs C32 to C39 should be left
open-circuit.
Using a 1 : 16 multiplex rate, two sets of row outputs are
driven, thus facilitating split-screen configurations, i.e. a
row select pulse appears simultaneously at R0 and
R16/C16, R1 and R17/C17 etc. Similarly, using a multiplex
rate of 1 : 8, four sets of row outputs are driven
simultaneously. Driver outputs must be connected directly
to the LCD. Unused outputs should be left open-circuit.
In 1 : 8 R0 to R7 are rows; in 1 : 16 R0 to R15/C15 are
rows; in 1 : 24 R0 to R23/C23 are rows; in 1 : 32
R0 to R31/C31 are rows.
Table 4 Signal frequencies required for nominal 64 Hz frame frequency; note 1.
Notes
1. A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
2. R
OSC
= 330 kΩ.
OSCILLATOR
FREQUENCY
f
OSC
(2)
(Hz)
FRAME FREQUENCY
f
SYNC
(Hz)
MULTIPLEX RATE (n)
DIVISION
RATIO
CLOCK FREQUENCY
f
CLK
(Hz)
12288 64 1 : 8, 1 : 16, 1 : 32 6 2048
12288 64 1 : 24 8 1536
2003 Apr 14 15
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
7.9 Display mode controller
The configuration of the outputs (row or column) and the
selection of the appropriate driver waveforms are
controlled by the display mode controller.
7.10 Display RAM
The PCF8578 contains a 32 × 40-bit static RAM which
stores the display data. The RAM is divided into 4 banks
of 40 bytes (4 × 8 × 40 bits). During RAM access, data is
transferred to/from the RAM via the I
2
C-bus. The first
eight columns of data (0 to 7) cannot be displayed but
are available for general data storage and provide
compatibility with the PCF8579. There is a direct
correspondence between X-address and column output
number.
7.11 Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows an individual
data byte or a series of data bytes to be written into, or read
from, the display RAM, controlled by commands sent on
the I
2
C-bus.
7.12 Subaddress counter
The storage and retrieval of display data is dependent on
the content of the subaddress counter. Storage takes
place only when the contents of the subaddress counter
agree with the hardware subaddress. The hardware
subaddress of the PCF8578, valid in mixed mode only, is
fixed at 0000.
7.13 I
2
C-bus controller
The I
2
C-bus controller detects the I
2
C-bus protocol, slave
address, commands and display data bytes. It performs
the conversion of the data input (serial-to-parallel) and the
data output (parallel-to-serial). The PCF8578 acts as an
I
2
C-bus slave transmitter/receiver in mixed mode, and as
a slave receiver in row mode. A slave device cannot
control bus communication.
7.14 Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.15 RAM access
RAM operations are only possible when the PCF8578 is
in mixed mode.
In this event its hardware subaddress is internally fixed at
0000 and the hardware subaddresses of any PCF8579
used in conjunction with the PCF8578 must start at 0001.
There are three RAM ACCESS modes:
• Character
• Half-graphic
• Full-graphic.
These modes are specified by bits G1 to G0 of the RAM
ACCESS command. The RAM ACCESS command
controls the order in which data is written to or read from
the RAM (see Fig.10).
To store RAM data, the user specifies the location into
which the first byte will be loaded (see Fig.11):
• Device subaddress (specified by the DEVICE SELECT
command)
• RAM X-address (specified by the LOAD X-ADDRESS
command)
• RAM bank (specified by bits Y1 and Y0 of the RAM
ACCESS command).
Subsequent data bytes will be written or read according to
the chosen RAM ACCESS mode. Device subaddresses
are automatically incremented between devices until the
last device is reached. If the last device has
subaddress 15, further display data transfers will lead to a
wrap-around of the subaddress to 0.
7.16 Display control
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The number of rows scanned depends on the multiplex
rate set by bits M1 and M0 of the SET MODE command.
The display status (all dots on/off and normal/inverse
video) is set by bits E1 and E0 of the SET MODE
command. For bank switching, the RAM bank
corresponding to the top of the display is set by bits
B1 and B0 of the SET START BANK command. This is
shown in Fig.12. This feature is useful when scrolling in
alphanumeric applications.
7.17 TEST pin
The TEST pin must be connected to V
SS
.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

PCF8578T/1,118

Mfr. #:
Buy PCF8578T/1,118
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers DOT MATRIX LCD DRIVER (R/COLM)
Lifecycle:
New from this manufacturer.
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