2003 Apr 14 7
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
Fig.3 Pin configuration (LQFP64).
handbook, full pagewidth
PCF8578H
MBH588
1
2
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5
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48
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33
17
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64
63
62
61
60
59
58
57
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55
54
53
52
51
50
49
SCL
CLK
TEST
SA0
n.c.
n.c.
OSC
V
SS
SYNC
SDA
R0
R1
R2
R3
R4
R5
R6
R7
R21/C21
R20/C20
R19/C19
R18/C18
R17/C17
R16/C16
R15/C15
R14/C14
R13/C13
R12/C12
R11/C11
R10/C10
R9/C9
R8/C8
R31/C31
C35
C34
C33
n.c.
C32
C39
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
V
LCD
V
DD
V
5
V
4
V
3
V
2
C38
C37
C36
R30/C30
R29/C29
R28/C28
R27/C27
R26/C26
R24/C24
R25/C25
R23/C23
n.c.
R22/C22
2003 Apr 14 8
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
7 FUNCTIONAL DESCRIPTION
The PCF8578 row/column driver is designed for use in one
of three ways:
Stand-alone row/column driver for small displays
(mixed mode)
Row/column driver with cascaded PCF8579s
(mixed mode)
Row driver with cascaded PCF8579s (mixed mode).
7.1 Mixed mode
In mixed mode, the device functions as both a row and
column driver. It can be used in small stand-alone
applications, or for larger displays with up to 15 PCF8579s
(31 PCF8579s when two slave addresses are used).
See Table 1 for common display configurations.
7.2 Row mode
In row mode, the device functions as a row driver with up
to 32 row outputs and provides the clock and
synchronization signals for the PCF8579. Up to 16
PCF8579s can normally be cascaded (32 when two slave
addresses are used).
Timing signals are derived from the on-chip oscillator,
whose frequency is determined by the value of the resistor
connected between OSC and V
SS
.
Commands sent on the I
2
C-bus from the host
microcontroller set the mode (row or mixed), configuration
(multiplex rate and number of rows and columns) and
control the operation of the device. The device may have
one of two slave addresses. The only difference between
these slave addresses is the least significant bit, which is
set by the logic level applied to SA0. The PCF8578 and
PCF8579 also have subaddresses. The subaddress of the
PCF8578 is only defined in mixed mode and is fixed at 0.
The RAM may only be accessed in mixed mode and data
is loaded as described for the PCF8579.
Bias levels may be generated by an external potential
divider with appropriate decoupling capacitors. For large
displays, bias sources with high drive capability should be
used. A typical mixed mode system operating with up to
15 PCF8579s is shown in Fig.5 (a stand-alone system
would be identical but without the PCF8579s).
Table 1 Possible displays configurations
Notes
1. Using 15 PCF8579s.
2. Using 16 PCF8579s.
APPLICATION
MULTIPLEX
RATE
MIXED MODE ROW MODE
TYPICAL APPLICATIONS
ROWS COLUMNS ROWS COLUMNS
Stand alone 1 : 8 8 32 −−small digital or
alphanumerical displays
1:16 16 24 −−
1:24 24 16 −−
1:32 32 8 −−
With PCF8579 1 : 8 8
(1)
632
(1)
8 × 4
(2)
640
(2)
alphanumeric displays and
dot matrix graphic displays
1:16 16
(1)
624
(1)
16 × 2
(2)
640
(2)
1:24 24
(1)
616
(1)
24
(2)
640
(2)
1:32 32
(1)
608
(1)
24
(2)
640
(2)
2003 Apr 14 9
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
7.3 Multiplexed LCD bias generation
The bias levels required to produce maximum contrast
depend on the multiplex rate and the LCD threshold
voltage (V
th
). V
th
is typically defined as the RMS voltage at
which the LCD exhibits 10% contrast. Table 2 shows the
optimum voltage bias levels for the PCF8578 as functions
of V
op
(V
op
=V
DD
V
LCD
), together with the discrimination
ratios (D) for the different multiplex rates. A practical value
for V
op
is obtained by equating V
off(rms)
with V
th
. Figure 4
shows the first 4 rows of Table 2 as graphs. Table 3 shows
the relative values of the resistors required in the
configuration of Fig.5 to produce the standard multiplex
rates.
Table 2 Optimum LCD voltages
Table 3 Multiplex rates and resistor values for Fig.5
7.4 Power-on reset
At power-on the PCF8578 resets to a defined starting
condition as follows:
1. Display blank
2. 1 : 32 multiplex rate, row mode
3. Start bank, 0 selected
4. Data pointer is set to X, Y address 0, 0
5. Character mode
6. Subaddress counter is set to 0
7. I
2
C-bus interface is initialized.
Data transfers on the I
2
C-bus should be avoided for 1 ms
following power-on, to allow completion of the reset action.
PARAMETER
MULTIPLEX RATE
1:8 1:16 1:24 1:32
0.739 0.800 0.830 0.850
0.522 0.600 0.661 0.700
0.478 0.400 0.339 0.300
0.261 0.200 0.170 0.150
0.297 0.245 0.214 0.193
0.430 0.316 0.263 0.230
1.447 1.291 1.230 1.196
3.370 4.080 4.680 5.190
RESISTORS
MULTIPLEX RATE (n)
n = 8 n = 16, 24, 32
R1 R R
R2 R
R3
V
2
V
op
---------
V
3
V
op
---------
V
4
V
op
---------
V
5
V
op
---------
V
off rms()
V
op
----------------------
V
on rms()
V
op
---------------------
D
V
on rms()
V
off rms()
----------------------
=
V
op
V
th
---------
n2()R
3n()R n3()R
Fig.4 V
bias
/V
op
as a function of the multiplex rate.
1:8 1:16 1:32
1.0
0
0.8
MSA838
1:24
0.6
0.4
0.2
multiplex rate
V
bias
V
op
V
5
V
4
V
3
V
2
V
bias
=V
2
, V
3
, V
4
, V
5
. See Table 2.

PCF8578T/1,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers DOT MATRIX LCD DRIVER (R/COLM)
Lifecycle:
New from this manufacturer.
Delivery:
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