2003 Apr 14 25
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
Fig.16 Definition of start and stop condition.
MBA608
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
Fig.17 System configuration.
MBA605
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
SDA
SCL
Fig.18 Acknowledgement on the I
2
C-bus.
The general characteristics and detailed specification of the I
2
C-bus are available on request.
handbook, full pagewidth
MBA606 - 1
START
condition
S
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
clock pulse for
acknowledgement
1
2
8
9
2003 Apr 14 26
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take
normal precautions appropriate to handling MOS devices (see
“Handling MOS devices”
).
SYMBOL PARAMETER MIN. MAX. UNIT
V
DD
supply voltage 0.5 +8.0 V
V
LCD
LCD supply voltage V
DD
11 V
DD
V
V
I1
input voltage SDA, SCL, CLK, TEST, SA0 and OSC V
SS
0.5 V
DD
+ 0.5 V
V
I2
input voltage V
2
to V
5
V
LCD
0.5 V
DD
+ 0.5 V
V
o1
output voltage SYNC and CLK V
SS
0.5 V
DD
+ 0.5 V
V
o2
output voltage R0 to R7, R8/C8 to R31/C31 and C32 to C39 V
LCD
0.5 V
DD
+ 0.5 V
I
I
DC input current 10 +10 mA
I
O
DC output current 10 +10 mA
I
DD
, I
SS
, I
LCD
V
DD
, V
SS
or V
LCD
current 50 +50 mA
P
tot
total power dissipation per package 400 mW
P
o
power dissipation per output 100 mW
T
stg
storage temperature 65 +150 °C
2003 Apr 14 27
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
12 DC CHARACTERISTICS
V
DD
= 2.5 to 6 V; V
SS
=0V;V
LCD
=V
DD
3.5 V to V
DD
9V;T
amb
= 40 to +85 °C; unless otherwise specified.
Notes
1. Outputs are open; inputs at V
DD
or V
SS
; I
2
C-bus inactive; external clock with 50% duty factor.
2. Resets all logic when V
DD
<V
POR
.
3. Periodically sampled; not 100% tested.
4. Resistance measured between output terminal (R0 to R7, R8/C8 to R31/C31 and C32 to C39) and bias input
(V
2
to V
5
, V
DD
and V
LCD
) when the specified current flows through one output under the following conditions
(see Table 2):
a) V
op
=V
DD
V
LCD
=9V.
b) Row mode, R0 to R7 and R8/C8 to R31/C31: V
2
V
LCD
6.65 V; V
5
V
LCD
2.35 V; I
LOAD
= 150 µA.
c) Column mode, R8/C8 to R31/C31 and C32 to C39: V
3
V
LCD
4.70 V; V
4
V
LCD
4.30 V; I
LOAD
= 100 µA.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
DD
supply voltage 2.5 6.0 V
V
LCD
LCD supply voltage V
DD
9 V
DD
3.5 V
I
DD1
supply current external clock f
CLK
= 2 kHz; note 1 615 µA
I
DD2
supply current internal clock R
OSC
= 330 kΩ−20 50 µA
V
POR
power-on reset level note 2 0.8 1.3 1.8 V
Logic
V
IL
LOW level input voltage V
SS
0.3V
DD
V
V
IH
HIGH level input voltage 0.7V
DD
V
DD
V
I
OL1
LOW level output current at SYNC
and CLK
V
OL
=1V; V
DD
=5V 1 −− mA
I
OH1
HIGH level output current at SYNC
and CLK
V
OH
=4V; V
DD
=5V −−1mA
I
OL2
LOW level output current at SDA V
OL
= 0.4 V; V
DD
=5V 3 −− mA
I
L1
leakage current at SDA, SCL, SYNC,
CLK, TEST and SA0
V
i
=V
DD
or V
SS
−−+1mA
I
L2
leakage current at OSC V
i
=V
DD
−−+1µA
C
i
input capacitance at SCL and SDA note 3 −−5pF
LCD outputs
I
L3
leakage current at V
2
to V
5
V
i
=V
DD
or V
LCD
2 −+2 µA
V
DC
DC component of LCD drivers
R0 to R7, R8/C8 to R31/C31 and
C32 to C39
−±20 mV
R
ROW
output resistance R0 to R7 and
R8/C8 to R31/C31
row mode; note 4 1.5 3 k
R
COL
output resistance R8/C8 to R31/C31
and C32 to C39
column mode; note 4 36 k

PCF8578T/1,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LCD Drivers DOT MATRIX LCD DRIVER (R/COLM)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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