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THERMAL DATA
Recommend Thermal Data for SOIC16 Package
Parameter Test Conditions Typical Value Units
minpad board (Note 6) 1”pad board (Note 7)
JunctiontoLead (psiJL, Y
JL
)
20 15 °C/W
JunctiontoAmbient (R
q
JA
, q
JA
)
100 83 °C/W
6. 1 oz. copper, 94 mm
2
copper area, 0.062” thick FR4.
7. 1 oz. copper, 767 mm
2
copper area, 0.062” thick FR4.
Figure 19. Min Pad PCB Layout
Figure 20. Min Pad PCB Layout
Figure 21. Internal Construction of the Package
(notice pins 4, 5 and 12, 13 are connected to flag)
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Table 1. SOIC 16Lead Thermal RC Network Models
96 mm
2
767 mm
2
96 mm
2
767 mm
2
Cu Area
Cauer network Foster network
C’s C’s Units Tau Tau units
1 1.84E06 1.84E06 Ws/C 2.99E07 2.99E07 sec
2 8.69E06 8.69E06 Ws/C 4.40E06 4.40E06 sec
3 2.61E05 2.61E05 Ws/C 4.62E05 4.62E05 sec
4 8.98E05 8.98E05 Ws/C 5.08E04 5.08E04 sec
5 2.30E03 2.30E03 Ws/C 8.93E03 8.95E03 sec
6 2.99E02 3.07E02 Ws/C 2.04E01 2.19E01 sec
7 1.79E01 1.90E01 Ws/C 3.26E+00 2.75E+00 sec
8 7.79E01 9.94E01 Ws/C 3.21E+01 2.19E+01 sec
9 5.34E+00 3.98E+00 Ws/C 1.24E+02 1.20E+02 sec
R’s R’s R’s R’s
1 0.199 0.199 C/W 0.123 0.123 C/W
2 0.598 0.598 C/W 0.349 0.349 C/W
3 1.795 1.795 C/W 1.057 1.057 C/W
4 4.085 4.085 C/W 4.61 4.61 C/W
5 3.977 3.977 C/W 3.87 3.89 C/W
6 7.509 7.833 C/W 5.77 5.99 C/W
7 19.886 15.247 C/W 13.17 11.38 C/W
8 40.307 24.781 C/W 28.85 15.52 C/W
9 18.193 21.446 C/W 38.75 37.05 C/W
NOTE: Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in
the Foster network are computed by the square root of time constant R(t) = 225 * sqrt(time(sec)). The constant is derived based
on the active area of the device with silicon and epoxy at the interface of the heat generation.
The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior
due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear
a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily
implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical
tools (for instance, in a spreadsheet program), according to the following formula:
R(t) +
n
S
i + 1
R
i
ǒ
1e
tń tau
i
Ǔ
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qJA vs Copper Spreader Area
70
75
80
85
90
95
100
0 100 200 300 400 500 600 700 800
Figure 22. SOIC 16Lead qJA as a Function of the
Pad Copper Area Including Traces, Board Material
1 oz
2 oz
qJA (°C/W)
COPPER AREA (mm
2
)
Figure 23. 16 Lead SOW (4 Leads Fused), qJA as
a Function of the Pad Copper Area (2 oz. Cu
Thickness), Board Material = 0.0625, G10/R4
40
70
90
100
THERMAL RESISTANCE,
JUNCTIONAMBIENT, R
q
JA
, (°C/W)
0
COPPER AREA (inch
2
)
0.5 1.0 1.5 2.0 3.0
80
60
50
2.5
0.1
1
10
100
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
Time (sec)
Figure 24. SOIC 16Lead Single Pulse Heating Curve
Cu Area 94 mm
2
Cu Area 767 mm
2
R(t) (°C/W)
0.1
1
10
100
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
Time (sec)
Figure 25. SOIC 16Lead Thermal Duty Cycle Curves on 1” Spreader Test Board
R(t) (°C/W)
Single
50% Duty Cycle
20%
10%
5%
1%
Cu Area 767 mm
2
, 1 oz Cu

NCV8508D2T50G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG LINEAR 5V 250MA D2PAK-7
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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