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Table 3. SOIC 8Lead EP Thermal RC Network Models
54 mm
2
717 mm
2
54 mm
2
717 mm
2
Cu Area
Cauer Network Foster Network
C’s C’s Units Tau Tau units
1 2.28E06 2.28E06 Ws/C 2.99E07 2.99E07 sec
2 1.08E05 1.08E05 Ws/C 4.40E06 4.40E06 sec
3 3.24E05 3.24E05 Ws/C 4.36E05 4.36E05 sec
4 9.71E05 9.71E05 Ws/C 3.59E04 3.74E04 sec
5 6.28E04 7.55E04 Ws/C 3.17E03 4.59E03 sec
6 7.13E03 1.49E02 Ws/C 0.030 0.162 sec
7 1.54E02 9.28E02 Ws/C 0.341 0.473 sec
8 6.16E02 1.72E01 Ws/C 2.909 1.653 sec
9 1.94E01 3.83E01 Ws/C 16.126 8.488 sec
10 1.52E+00 2.41E+00 Ws/C 54.334 71.562 sec
R’s R’s R’s R’s
1 0.161 0.161 C/W 0.11 0.11 C/W
2 0.482 0.482 C/W 0.26 0.26 C/W
3 1.445 1.445 C/W 0.73 0.73 C/W
4 3.00 3.00 C/W 2.60 2.83 C/W
5 4.47 5.34 C/W 4.80 5.82 C/W
6 5.92 12.21 C/W 2.98 8.95 C/W
7 20.11 16.03 C/W 12.20 0.61 C/W
8 51.85 4.89 C/W 26.10 12.91 C/W
9 68.87 15.34 C/W 62.22 16.96 C/W
10 27.52 22.36 C/W 71.83 32.09 C/W
NOTE: Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in
the Foster network are computed by the square root of time constant R(t) = 225 * sqrt(time(sec)). The constant is derived based
on the active area of the device with silicon and epoxy at the interface of the heat generation.
The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior
due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear
a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily
implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical
tools (for instance, in a spreadsheet program), according to the following formula:
R(t) +
n
S
i + 1
R
i
ǒ
1e
tń tau
i
Ǔ
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qJA vs Copper Spreader Area
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
0 50 100150200250300350400450500550600650700750800
qJA (°C/W)
COPPER AREA (mm
2
)
Figure 35. SOIC 8Lead EP qJA as a Function of the
Pad Copper Area Including Traces, Board Material
1 oz
2 oz
0.1
1
10
100
1000
0.000001 0.00001 0.0001 0.001
0.01
0.1
1 10 100 1000
Time (sec)
Cu Area 54 mm
2
Cu Area 717 mm
2
R(t) (°C/W)
Figure 36. SOIC 8Lead EP Single Pulse Heating Curve
0.1
1
10
100
0.000001 0.00001 0.0001 0.001
0.01
0.1
1 10 100 1000
Time (sec)
R(t) (°C/W)
Single
50% Duty Cycle
20%
10%
5%
1%
Cu Area 767 mm
2
, 1 oz Cu
Figure 37. SOIC 8Lead Thermal Duty Cycle Curves on 1” Spreader Test Board
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21
Junction
R
1
C
1
C
2
R
2
C
3
R
3
C
n
R
n
Time constants are not simple RC products. Amplitudes
of mathematical solution are not the resistance values.
Ambient
(thermal ground)
Figure 38. Grounded Capacitor Thermal Network (“Cauer” Ladder)
Junction
R
1
C
1
C
2
R
2
C
3
R
3
C
n
R
n
Each rung is exactly characterized by its RCproduct
time constant; amplitudes are the resistances.
Ambient
(thermal ground)
Figure 39. NonGrounded Capacitor Thermal Ladder (“Foster” Ladder)

NCV8508D2T50G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG LINEAR 5V 250MA D2PAK-7
Lifecycle:
New from this manufacturer.
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