LTC4009IUF-2#TRPBF Datasheet LTC4009IUF#PBF, LTC4009CUF#PBF, LTC4009IUF-2#PBF | P22-P24

LTC4009

LTC4009-1/LTC4009-2

4009fd

where Q

is the rated gate charge of the top external NFET

with V

= 4.5V. The maximum average diode current is

then given by:

= Q

• 665kHz

To improve efficiency by increasing V

applied to the top

FET, substitute a Schottky diode with low reverse leakage

for D1.

PWM jitter has been observed in some designs operating

at higher V

OUT

ratios. This jitter does not substantially

affect DC charge current accuracy. A series resistor with a

value of 5Ω to 20Ω can be inserted between the cathode

of D1 and the BOOST pin to remove this jitter if present.

A resistor case size of 0603 or larger is recommended to

lower ESL and achieve the best results.

FET Selection

Two external power MOSFETs must be selected for use

with the charger: an N-channel power switch (top FET)

and an N-channel synchronous rectifier (bottom FET).

Peak gate-to-source drive levels are internally set to about

5V. Consequently, logic-level FETs must be used. In addi-

tion to the fundamental DC current, selection criteria for

these MOSFETs also include channel resistance R

DS(ON)

total gate charge Q

, reverse transfer capacitance C

RSS

maximum rated drain-source voltage BV

DSS

and switching

characteristics such as t

d(ON/OFF)

. Power dissipation for

each external FET is given by:

V I T R

k V

D TOP

BAT MAX DS ON

CLP

( )

• •

•

( )

1 δ∆

LLP MAX RSS

D BOT

CLP BAT M

I C kHz

V V I

665• • •

– •

( )

AAX DS ON

CLP

T R

1•

( )

δ∆

where δ is the temperature dependency of R

DS(ON)

, ∆T

is the temperature rise above the point specified in the

FET data sheet for R

DS(ON)

and k is a constant inversely

related to the internal LTC4009 top gate driver. The term

(1 + δ

∆

T) is generally given for a MOSFET in the form

of a normalized R

DS(ON)

curve versus temperature, but

δ of 0.005/°C can be used as a suitable approximation

for logic-level FETs if other data is not available. C

RSS

/dV

is usually specified in the MOSFET character-

istics. The constant k = 2 can be used in estimating top

FET dissipation. The LTC4009 is designed to work best

with external FET switches with a total gate charge at 5V

of 15nC or less.

For V

CLP

< 20V, high charge current efficiency generally

improves with larger FETs, while for V

CLP

> 20V, top gate

transition losses increase rapidly to the point that using

a topside NFET with higher R

DS(ON)

but lower C

RSS

can

actually provide higher efficiency. If the charger will be

operated with a duty cycle above 85%, overall efficiency

is normally improved by using a larger top FET.

The synchronous (bottom) FET losses are greatest at high

input voltage or during a short circuit, which forces a low

side duty cycle of nearly 100%. Increasing the size of this

FET lowers its losses but increases power dissipation in the

LTC4009. Using asymmetrical FETs will normally achieve

cost savings while allowing optimum efficiency.

Select FETs with BV

DSS

that exceeds the maximum V

CLP

voltage that will occur. Both FETs are subjected to this level

of stress during operation. Many logic-level MOSFETs are

limited to 30V or less.

applicaTions inForMaTion

4009fd

LTC4009

LTC4009-1/LTC4009-2

The LTC4009 uses an improved adaptive TGATE and

BGATE drive that is insensitive to MOSFET inertial delays,

d(ON/OFF)

to avoid overlap conduction losses. Switching

characteristics from power MOSFET data sheets apply

only to a specific test fixture, so there is no substitute for

bench evaluation of external FETs in the target application.

In general, MOSFETs with lower inertial delays will yield

higher efficiency.

Diode Selection

A Schottky diode in parallel with the bottom FET and/or

top FET in an LTC4009 application clamps SW during the

non-overlap times between conduction of the top and

bottom FET switches. This prevents the body diode of the

MOSFETs from forward biasing and storing charge, which

could reduce efficiency as much as 1%. One or both diodes

can be omitted if the efficiency loss can be tolerated. A 1A

Schottky is generally a good size for 3A chargers due to the

low duty cycle of the non-overlap times. Larger diodes can

actually result in additional efficiency (transition) losses

due to larger junction capacitance.

Loop Compensation and Soft-Start

The three separate PWM control loops of the LTC4009

can be compensated by a single set of components at-

tached between the ITH pin and GND. As shown in the

typical LTC4009 application, a 6.04k resistor in series

with a capacitor of at least 0.1µF provides adequate loop

compensation for the majority of applications.

The LTC4009 can be soft-started with the compensation

capacitor on the ITH pin. At start-up, ITH will quickly rise

to about 0.25V, then ramp up at a rate set by the com-

pensation capacitor and the 40µA ITH bias current. The

full programmed charge current will be reached when ITH

reaches approximately 2V. With a 0.1µF capacitor, the time

to reach full charge current is usually greater than 1.5ms.

This capacitor can be increased if longer start-up times

are required, but loop bandwidth and dynamic response

will be reduced.

INTV

Regulator Output

Bypass the INTV

regulator output to GND with a low

ESR X5R or X7R ceramic capacitor with a value of 0.47µF

or larger. The capacitor used to build the BOOST supply

(C2 in Figure 11) can serve as this bypass. Do not draw

more than 30mA from this regulator for the host system,

governed by IC power dissipation.

Calculating IC Power Dissipation

The user should ensure that the maximum rated junction

temperature is not exceeded under all operating conditions.

The thermal resistance of the LTC4009 package (θ

) is

37°C/W, provided the Exposed Pad is in good thermal

contact with the PCB. The actual thermal resistance in

the application will depend on forced air cooling and other

heat sinking means, especially the amount of copper on

the PCB to which the LTC4009 is attached. The following

formula may be used to estimate the maximum average

power dissipation P

(in watts) of the LTC4009, which is

dependent upon the gate charge of the external MOSFETs.

This gate charge, which is a function of both gate and drain

voltage swings, is determined from specifications or graphs

in the manufacturer’s data sheet. For the equation below,

find the gate charge for each transistor assuming 5V gate

swing and a drain voltage swing equal to the maximum

CLP

voltage. Maximum LTC4009 power dissipation under

normal operating conditions is then given by:

= DCIN(2.8mA + I

+ 665kHz(Q

TGATE

+ Q

BGATE

))

– 5I

where:

= Average external INTV

load current, if any

TGATE

= Gate charge of external top FET in Coulombs

BGATE

= Gate charge of external bottom FET in

Coulombs

applicaTions inForMaTion

LTC4009

LTC4009-1/LTC4009-2

4009fd

PCB Layout Considerations

To prevent magnetic and electrical field radiation and

high frequency resonant problems, proper layout of the

components connected to the LTC4009 is essential. Refer

to Figure 12. For maximum efficiency, the switch node

rise and fall times should be minimized. The following

PCB design priority list will help insure proper topology.

Layout the PCB using this specific order.

Input

capacitors should be placed as close as possible

to switching FET supply and ground connections with

the shortest copper traces possible. The switching

FETs must be on the same layer of copper as the input

capacitors. Vias should not be used to make these

connections.

Place

the LTC4009 close to the switching FET gate

terminals, keeping the connecting traces short to

produce clean drive signals. This rule also applies to IC

supply and ground pins that connect to the switching

FET source pins. The IC can be placed on the opposite

side of the PCB from the switching FETs.

Place

the inductor input as close as possible to the

switching FETs. Minimize the surface area of the switch

node. Make the trace width the minimum needed to

support the programmed charge current. Use no cop-

per fills or pours. Avoid running the connection on

multiple copper layers in parallel. Minimize capacitance

from the switch node to any other trace or plane.

Place

the charge current sense resistor immediately

adjacent to the inductor output, and orient it such

that current sense traces to the LTC4009 are not long.

These feedback traces need to be run together as a

single pair with the smallest spacing possible on any

given layer on which they are routed. Locate any filter

component on these traces next to the LTC4009, and

not at the sense resistor location.

Place

output capacitors adjacent to the sense resistor

output and ground.

6. Output capacitor ground connections must feed into

the same copper that connects to the input capacitor

ground before connecting back to system ground.

7. Connection

of switching ground to system ground,

or any internal ground plane, should be single-point.

If the system has an internal system ground plane,

a good way to do this is to cluster vias into a single

star point to make the connection.

Route analog ground as a trace tied back to the LTC4009

GND paddle before connecting to any other ground.

Avoid using the system ground plane. A useful CAD

technique is to make analog ground a separate ground

net and use a 0Ω resistor to connect analog ground

to system ground.

good rule of thumb for via count in a given high

current path is to use 0.5A per via. Be consistent when

applying this rule.

Figure 12. High Speed Switching Path

4009 F12

BAT

SENSE

HIGH

FREQUENCY

CIRCULATING

PATH

BAT

ANALOG

GROUND

SYSTEM

GROUND

SWITCH NODE

SWITCHING GROUND

OUT

GND

applicaTions inForMaTion

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

LTC4009IUF-2#TRPBF

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Manufacturer:

Analog Devices / Linear Technology

Description:

Battery Management High Efficiency, Multi-Chemistry QFN Battery Charger

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