25
4009fd
LTC4009
LTC4009-1/LTC4009-2
Figure 13. Kelvin Sensing of Charge Current
TO CSP
R
IN
4009 F13
DIRECTION OF CHARGING CURRENT
R
SENSE
TO CSN
R
IN
10. If possible, place all the parts listed above on the same
PCB layer.
11. C
opper fills or pours are good for all power connections
except as noted above in Rule 3. Copper planes on
multiple layers can also be used in parallel. This helps
with thermal management and lowers trace inductance,
which further improves EMI performance.
12.
For best current programming accuracy, provide a
Kelvin connection from R
SENSE
to CSP and CSN. See
Figure 13 for an example.
13. It
is important to minimize parasitic capacitance on
the CSP and CSN pins. The traces connecting these
pins to their respective resistors should be as short
as possible.
applicaTions inForMaTion
LTC4009
LTC4009-1/LTC4009-2
26
4009fd
package DescripTion
4.00 ± 0.10
4.00 ± 0.10
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
2019
1
2
BOTTOM VIEW—EXPOSED PAD
2.00 REF
2.45 ± 0.10
0.75 ± 0.05
R = 0.115
TYP
R = 0.05
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF20) QFN 01-07 REV A
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.00 REF
2.45 ± 0.05
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
2.45 ± 0.10
2.45 ± 0.05
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
27
4009fd
LTC4009
LTC4009-1/LTC4009-2
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
D 3/10 I-Grade Parts Added. Reflected Throughout the Data Sheet 1 to 28
(Revision history begins at Rev D)

LTC4009IUF-2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management High Efficiency, Multi-Chemistry QFN Battery Charger
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New from this manufacturer.
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