ISL12027AIB27Z-T Datasheet ISL12027IB27AZ, ISL12027IVZ-T, ISL12027IBAZ | P13-P15

FN8232.8

August 12, 2010

Alarm Registers (Non-Volatile)

Alarm0 and Alarm1

The alarm register bytes are set up identical to the RTC

an enable bit (enable = “1”). These enable bits specify which

alarm registers (seconds, minutes, etc.) are used to make

the comparison. Note that there is no alarm byte for year.

The alarm function works as a comparison between the

alarm registers and the RTC registers. As the RTC

advances, the alarm will be triggered once a match occurs

between the alarm registers and the RTC registers. Any one

alarm register, multiple registers, or all registers can be

enabled for a match. See “Device Operation” on page 14

and “Application Section” on page 22 for more information.

Control Registers (Non-Volatile)

The Control Bits and Registers described in the following

section are non-volatile.

BL Register

BP2, BP1, BP0 - Block Protect Bits

The Block Protect Bits, BP2, BP1 and BP0, determine which

blocks of the array are write protected. A write to a protected

block of memory is ignored. The block protect bits will

prevent write operations to one of eight segments of the

array. The partitions are described in Table 3.

Oscillator Compensation Registers

There are two trimming options.

• ATR. Analog Trimming Register

• DTR. Digital Trimming Register

These registers are non-volatile. The combination of analog

and digital trimming can give up to -64 to +110ppm of total

adjustment.

ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,

ATR0: Analog Trimming Register

Six analog trimming bits, ATR0 to ATR5, are provided in

order to adjust the on-chip load capacitance value for

frequency compensation of the RTC. Each bit has a different

weight for capacitance adjustment. For example, using a

Citizen CFS-206 crystal with different ATR bit combinations

provides an estimated ppm adjustment range from -34ppm

to +80ppm to the nominal frequency compensation.

The effective on-chip series load capacitance, C

LOAD

ranges from 4.5pF to 20.25pF with a mid-scale value of

12.5pF (default). C

LOAD

is changed via two digitally

controlled capacitors, C

and C

, connected from the X1

and X2 pins to ground (see Figure 12). The value of C

and

is given Equation 1:

The effective series load capacitance is the combination of

and C

For example, C

LOAD

(ATR = 00000) = 12.5pF,

LOAD

(ATR = 100000) = 4.5pF, and

LOAD

(ATR = 011111) = 20.25pF. The entire range for the

series combination of load capacitance goes from 4.5pF to

20.25pF in 0.25pF steps. Note that these are typical values.

DTR Register - DTR2, DTR1, DTR0: Digital

Trimming Register

The digital trimming Bits DTR2, DTR1 and DTR0 adjust the

number of counts per second and average the ppm error to

achieve better accuracy.

DTR2 is a sign bit. DTR2 = 0 means frequency

compensation is >0. DTR2 = 1 means frequency

compensation is <0.

DTR1 and DTR0 are scale bits. DTR1 gives 10ppm

adjustment and DTR0 gives 20ppm adjustment.

A range from -30ppm to +30ppm can be represented by

using the three DTR bits.

TABLE 3.

BP2

BP1

BP0

PROTECTED ADDRESSES

ISL12027 ARRAY LOCK

0 0 0 None (Default) None

0 0 1 180

– 1FF

Upper 1/4

0 1 0 100

– 1FF

Upper 1/2

0 1 1 000

– 1FF

Full Array

100 000

– 03F

First 4 Pages

101 000

– 07F

First 8 Pages

1 1 0 000

– 0FF

First 16 Pages

1 1 1 000

– 1FF

Full Array

FIGURE 12. DIAGRAM OF ATR

CRYSTAL

OSCILLATOR

16 b5⋅ 8b4 4b3 2b2 1b1 0.5b0 9+⋅+⋅+⋅+⋅+⋅+()pF=

(EQ. 1)

LOAD

-----------

⎝⎠

⎛⎞

-----------------------------------

LOAD

16 b5

⋅ 8 b4 4 b3 2 b2 1 b1 0.5 b0 9+⋅+⋅+⋅+⋅+⋅+

-----------------------------------------------------------------------------------------------------------------------------

⎝⎠

⎛⎞

(EQ. 2)

ISL12027, ISL12027A

FN8232.8

August 12, 2010

PWR Register: SBIB, BSW, VTS2, VTS1, VTS0

SBIB: Serial Bus Interface (Enable)

The serial bus can be disabled in battery backup mode by

setting this bit to “1”. This will minimize power drain on the

battery. The Serial Interface can be enabled in battery

backup mode by setting this bit to “0” (default is “0”). See

“Power Control Operation” on page 15 and “RESET” on

page 9.

BSW: Power Control Bit

The Power Control bit, BSW, determines the conditions for

switching between V

and Backup Battery. There are two

options:

Option 1. Standard: Set “BSW = 0” (default for ISL12027A)

Option 2. Legacy /Default Mode: Set “BSW = 1” (default

for ISL12027)

See “Power Control Operation” on page 15 for more details.

Also see “I

C Communications During Battery Backup and

LVR Operation” on page 24 for important details.

VTS2, VTS1, VTS0: V

RESET

Select Bits

The ISL12027 is shipped with a default V

threshold

RESET

) per the “Ordering Information” table on page 2.

This register is a non-volatile with no protection, therefore

any writes to this location can change the default value from

that marked on the package. If not changed with a non-

volatile write, this value will not change over normal

operating and storage conditions. However, ISL12027 has

four (4) additional selectable levels to fit the customers

application. Levels are: 4.64V (default), 4.38V, 3.09V, 2.92V

and 2.63V. The V

RESET

selection is via 3 bits (VTS2, VTS1

and VTS0). See Table 5.

Care should be taken when changing the V

RESET

select bits.

If the V

RESET

voltage selected is higher than V

, then the

device will go into RESET and unless V

is increased, the

device will no longer be able to communicate using the I

bus.

In battery mode, the RESET signal output is asserted LOW

when the VDD voltage supply has dipped below the V

RESET

threshold, but the RESET

signal output will not return HIGH

until the device is back to V

mode even the V

voltage is

above V

RESET

threshold.

Device Operation

Writing to the Clock/Control Registers

Changing any of the bits of the clock/control registers

requires the following steps:

1. Write a 02h to the Status Register to set the Write Enable

Latch (WEL). This is a volatile operation, so there is no

delay after the write. (Operation preceded by a start and

ended with a stop).

2. Write a 06h to the Status Register to set both the Register

Write Enable Latch (RWEL) and the WEL bit. This is also

a volatile cycle. The zeros in the data byte are required.

(Operation proceeded by a start and ended with a stop).

Write all 8 bytes to the RTC registers, or one byte to the SR,

or one to five bytes to the control registers. This sequence

starts with a start bit, requires a slave byte of “11011110” and

an address within the CCR and is terminated by a stop bit. A

write to the EEPROM registers in the CCR will initiate a

non-volatile write cycle and will take up to 20ms to complete.

A write to the RTC registers (SRAM) will require much

shorter cycle time (t = t

BUF

). Writes to undefined areas have

no effect. The RWEL bit is reset by the completion of a write

to the CCR, so the sequence must be repeated to again

initiate another change to the CCR contents. If the sequence

is not completed for any reason (by sending an incorrect

number of bits or sending a start instead of a stop, for

example) the RWEL bit is not reset and the device remains

in an active mode. Writing all zeros to the status register

resets both the WEL and RWEL bits. A read operation

occurring between any of the previous operations will not

interrupt the register write operation.

Alarm Operation

Since the alarm works as a comparison between the alarm

registers and the RTC registers, it is ideal for notifying a host

processor of a particular time event and trigger some action as

a result. The host can be notified by polling the Status Register

(SR) Alarm bits. These two volatile bits (AL1 for Alarm 1 and

AL0 for Alarm 0), indicate if an alarm has happened. The AL1

and AL0 bits in the status register are reset by the falling edge

of the eighth clock of status register read.

TABLE 4. DIGITAL TRIMMING REGISTERS

DTR REGISTER

ESTIMATED FREQUENCY

PPMDTR2 DTR1 DTR0

000 0

010 +10

001 +20

011 +30

100 0

110 -10

101 -20

111 -30

TABLE 5.

VTS2 VTS1 VTS0 V

RESET

0 0 0 4.64V

0 0 1 4.38V

0 1 0 3.09V

0 1 1 2.92V

1 0 0 2.63V

ISL12027, ISL12027A

FN8232.8

August 12, 2010

There are two alarm operation modes: Single Event and

periodic Interrupt Mode:

1. Single Event Mode is enabled by setting the AL0E or

AL1E bit to “1”, the IM bit to “0”, and disabling the

frequency output. This mode permits a one-time match

between the alarm registers and the RTC registers. Once

this match occurs, the AL0 or AL1 bit is set to “1”. Once

the AL0 or AL1 bit is read, this will automatically reset it.

Both Alarm registers can be set at the same time to

trigger alarms. Polling the SR will reveal which alarm has

been set.

2. Interrupt Mode (or “Pulsed Interrupt Mode” or PIM) is

enabled by setting the AL0E or AL1E bit to “1” the IM bit

to “1”, and disabling the frequency output. If both AL0E

and AL1E bits are set to 1, then only the AL0E PIM alarm

will function (AL0E overrides AL1E). This means that

once the interrupt mode alarm is set, it will continue to

alarm for each occurring match of the alarm and present

time. This mode is convenient for hourly or daily

hardware interrupts in microcontroller applications such

as security cameras or utility meter reading. Interrupt

Mode CANNOT be used for general periodic alarms,

however, since a specific time period cannot be

programmed for interrupt, only matches to a specific time

of day. The interrupt mode is only stopped by disabling

the IM bit or the Alarm Enable bits.

Writing to the Alarm Registers

The Alarm Registers are non-volatile but require special

attention to insure a proper non-volatile write takes place.

Specifically, byte writes to individual registers are good for all

but registers 0006h and 0000Eh, which are the DWA0 and

DWA1 registers, respectively. Those registers will require a

special page write for non-volatile storage. The

recommended page write sequences are as follows:

1. 16-byte page writes: The best way to write or update the

Alarm Registers is to perform a 16-byte write beginning at

address 0001h (MNA0) and wrapping around and ending

at address 0000h (SCA0). This will insure that

non-volatile storage takes place. This means that the

code must be designed so that the Alarm0 data is written

starting with Minutes register, and then all the Alarm1

data, with the last byte being the Alarm0 Seconds (the

page ends at the Alarm1 Y2k register and then wraps

around to address 0000h).

Alternatively, the 16-byte page write could start with

address 0009h, wrap around and finish with address

0008h. Note that any page write ending at address

0007h or 000Fh (the highest byte in each Alarm) will not

trigger a non-volatile write, so wrapping around or

overlapping to the following Alarm's Seconds register is

advised.

2. Other non-volatile writes: It is possible to do writes of

less than an entire page, but the final byte must always

be addresses 0000h through 0004h or 0008h though

000Ch to trigger a non-volatile write. Writing to those

blocks of 5 bytes sequentially, or individually, will trigger a

non-volatile write. If the DWA0 or DWA1 registers need to

be set, then enough bytes will need to be written to

overlap with the other Alarm register and trigger the

non-volatile write. For Example, if the DWA0 register is

being set, then the code can start with a multiple byte

write beginning at address 0006h, and then write 3 bytes

ending with the SCA1 register as follows:

Addr Name

0006h DWA0

0007h Y2K0

0008h SCA1

If the Alarm1 is used, SCA1 would need to have the correct

data written.

Power Control Operation

The power control circuit accepts a V

and a V

BAT

input.

Many types of batteries can be used with Intersil RTC

products. For example, 3.0V or 3.6V Lithium batteries are

appropriate, and battery sizes are available that can power

an Intersil RTC device for up to 10 years. Another option is

to use a SuperCap for applications where V

is interrupted

for up to a month. See “Application Section” on page 22 for

more information.

There are two options for setting the change-over conditions

from V

to Battery backup mode. The BSW bit in the PWR

Option 1 - Standard Mode: Set “BSW = 0” (default for

ISL12027A)

Option 2 - Legacy/Default Mode: Set “BSW = 1” (default for

ISL12027)

Note that applications that have V

BAT

> V

will require

theISL12027A (standard mode) for proper start-up. The I

bus may or may not be operational during battery backup;

that function is controlled by the SBIB bit. That operation is

covered after the power control section.

OPTION 1 - STANDARD POWER CONTROL MODE

(ISL12027A)

In the Standard mode, the supply will switch over to the

battery when V

drops below V

TRIP

or V

BAT

, whichever is

lower. In this mode, accidental operation from the battery is

prevented since the battery backup input will only be used

when the V

supply is shut off.

To select Option 1, BSW bit in the Power Register must be

set to “BSW = 0”. A description of power switchover follows.

TABLE 6. V

BAT

TRIP POINT WITH DIFFERENT BSW SETTING

BSW BIT

BAT

TRIP

POINT (V) POWER CONTROL SETTING

0 2.2 Standard Mode (ISL12027A)

1 0 Legacy Mode (ISL12027)

ISL12027, ISL12027A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

ISL12027AIB27Z-T

Mfr. #:

Buy ISL12027AIB27Z-T

Manufacturer:

Renesas / Intersil

Description:

Real Time Clock REAL TIME CLK/CLNDR W/EEPROM 2 63VSET

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