ISL12027AIB27Z-T Datasheet ISL12027IB27AZ, ISL12027IVZ-T, ISL12027IBAZ | P22-P24

FN8232.8

August 12, 2010

Application Section

Crystal Oscillator and Temperature Compensation

Intersil has now integrated the oscillator compensation

circuity on-chip, to eliminate the need for external

components and adjust for crystal drift over-temperature and

enable very high accuracy time keeping (<5ppm drift).

The Intersil RTC family uses an oscillator circuit with on-chip

crystal compensation network, including adjustable

load-capacitance. The only external component required is

the crystal. The compensation network is optimized for

operation with certain crystal parameters which are common

in many of the surface mount or tuning-fork crystals available

today. Table 8 summarizes these parameters.

Table 9 contains some crystal manufacturers and part numbers

that meet the requirements for the Intersil RTC products.

The turnover temperature in Table 8 describes the

temperature where the apex of the of the drift vs temperature

curve occurs. This curve is parabolic with the drift increasing

as (T - T0)

. For an Epson MC-405 device, for example, the

turnover temperature is typically +25°C, and a peak drift of

>110ppm occurs at the temperature extremes of -40°C and

+85°C. It is possible to address this variable drift by adjusting

the load capacitance of the crystal, which will result in

predictable change to the crystal frequency. The Intersil RTC

family allows this adjustment over temperature since the

devices include on-chip load capacitor trimming. This control

is handled by the Analog Trimming Register, or ATR, which

has 6-bits of control. The load capacitance range covered by

the ATR circuit is approximately 3.25pF to 18.75pF, in

0.25pF increments. Note that actual capacitance would also

include about 2pF of package related capacitance. In-circuit

tests with commercially available crystals demonstrate that

this range of capacitance allows frequency control from

+116ppm to -37ppm, using a 12.5pF load crystal.

In addition to the analog compensation afforded by the

adjustable load capacitance, a digital compensation feature

is available for the Intersil RTC family. There are 3-bits

known as the Digital Trimming Register or DTR, and they

operate by adding or skipping pulses in the clock signal. The

range provided is ±30ppm in increments of 10ppm. The

default setting is 0ppm. The DTR control can be used for

coarse adjustments of frequency drift over-temperature or

for crystal initial accuracy correction.

A final application for the ATR control is in-circuit calibration for

high accuracy applications, along with a temperature sensor

chip. Once the RTC circuit is powered up with battery backup,

and frequency drift is measured. The ATR control is then

adjusted to a setting, which minimizes drift. Once adjusted at a

particular temperature, it is possible to adjust at other discrete

temperatures for minimal overall drift, and store the resulting

settings in the EEPROM. Extremely low overall temperature

drift is possible with this method. The Intersil evaluation board

contains the circuitry necessary to implement this control.

Layout Considerations

The crystal input at X1 has a very high impedance and will pick

up high frequency signals from other circuits on the board.

Since the X2 pin is tied to the other side of the crystal, it is also

a sensitive node. These signals can couple into the oscillator

SLAVE

ADDRESS

WORD

ADDRESS 1

SLAVE

ADDRESS

DATA

SDA BUS

SIGNALS FROM

THE SLAVE

SIGNALS FROM

THE MASTER

WORD

ADDRESS 0

1111

0000000

FIGURE 25. RANDOM ADDRESS READ SEQUENCE

DATA

(2)

SLAVE

ADDRESS

DATA

(n)

SDA BUS

SIGNALS FROM

THE SLAVE

SIGNALS

FROM

THE MASTER

DATA

(n - 1)

(n IS ANY INTEGER GREATER THAN 1)

DATA

(1)

FIGURE 26. SEQUENTIAL READ SEQUENCE

ISL12027, ISL12027A

FN8232.8

August 12, 2010

circuit and produce double clocking or mis-clocking, seriously

affecting the accuracy of the RTC. Care needs to be taken in

layout of the RTC circuit to avoid noise pickup. Figure 27 shows

a suggested layout for the ISL12027 or ISL12026 devices.

The X1 and X2 connections to the crystal are to be kept as

short as possible. A thick ground trace around the crystal is

advised to minimize noise intrusion, but ground near the X1

and X2 pins should be avoided as it will add to the load

capacitance at those pins. Keep in mind these guidelines for

other PCB layers in the vicinity of the RTC device. A small

decoupling capacitor at the V

pin of the chip is mandatory,

with a solid connection to ground (see Figure 27).

Oscillator Measurements

When a proper crystal is selected and the layout guidelines

above are observed, the oscillator should start up in most

circuits in less than one second. Some circuits may take slightly

longer, but start-up should definitely occur in less than 5s.

When testing RTC circuits, the most common impulse is to

apply a scope probe to the circuit at the X2 pin (oscillator

output) and observe the waveform. DO NOT DO THIS!

Although in some cases you may see a usable waveform, due

to the parasitics (usually 10pF to ground) applied with the

scope probe, there will be no useful information in that

waveform other than the fact that the circuit is oscillating. The

X2 output is sensitive to capacitive impedance so the voltage

levels and the frequency will be affected by the parasitic

elements in the scope probe. Applying a scope probe can

possibly cause a faulty oscillator to start-up, hiding other issues

(although in the Intersil RTC’s, the internal circuitry assures

startup when using the proper crystal and layout).

The best way to analyze the RTC circuit is to power it up and

read the real time clock as time advances. Alternatively the

frequency can be checked by setting an alarm for each minute.

Using the pulse interrupt mode setting, the once-per-minute

interrupt functions as an indication of proper oscillation.

Backup Battery Operation

Many types of batteries can be used with the Intersil RTC

products. 3.0V or 3.6V Lithium batteries are appropriate, and

sizes are available that can power a Intersil RTC device for

up to 10 years. Another option is to use a supercapacitor for

applications where V

may disappear intermittently for

short periods of time. Depending on the value of

TABLE 8. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTC’S

PARAMETER MIN TYP MAX UNITS NOTES

Frequency 32.768 kHz

Frequency Tolerance ±100 ppm Down to 20ppm if desired

Turnover Temperature 20 25 30 °C Typically the value used for most crystals

Operating Temperature Range -40 85 °C

Parallel Load Capacitance 12.5 pF

Equivalent Series Resistance 50 k

Ω For best oscillator performance

TABLE 9. CRYSTAL MANUFACTURERS

MANUFACTURER PART NUMBER TEMP RANGE (°C) +25°C FREQUENCY TOLERANCE (ppm)

Citizen CM201, CM202, CM200S -40 to +85 ±20

Epson MC-405, MC-406 -40 to +85 ±20

Raltron RSM-200S-A or B -40 to +85 ±20

SaRonix 32S12A or B -40 to +85 ±20

Ecliptek ECPSM29T-32.768K -10 to +60 ±20

ECS ECX-306/ECX-306I -10 to +60 ±20

Fox FSM-327 -40 to +85 ±20

FIGURE 27. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8

01µF

ISL12027

XTAL1

32.768kH

10k

ISL12027, ISL12027A

FN8232.8

August 12, 2010

supercapacitor used, backup time can last from a few days

to two weeks (with >1F). A simple silicon or Schottky barrier

diode can be used in series with V

to charge the

supercapacitor, which is connected to the V

BAT

pin. Try to

use Schottky diodes with very low leakages, <1µA

desirable.

Do not use the diode to charge a battery (especially lithium

batteries!).

Note that whether a battery or supercap is used, if the V

BAT

voltage drops below the data sheet minimum of 1.8V and the

power cycles to 0V then back to V

voltage, then the

RESET

output may stay low and the I

C communications will

not operate. The V

BAT

and V

power will need to be cycled

to 0V together to allow normal operation again.

There are two possible modes for battery backup operation,

Standard and Legacy mode. In Standard mode, there are no

operational concerns when switching over to battery backup

since all other devices functions are disabled. Battery drain

is minimal in Standard mode, and return to Normal V

powered operations predictable. In Legacy modes the V

BAT

pin can power the chip if the voltage is above V

and

TRIP

This makes it possible to generate alarms and

communicate with the device under battery backup, but the

supply current drain is much higher than the Standard mode

and backup time is reduced. During initial power-up, the

default mode is the Legacy mode.

C Communications During Battery Backup and

LVR Operation

Operation in Battery Backup mode and LVR is affected by

the BSW and SBIB bits as described earlier. These bits allow

flexible operation of the serial bus and EEPROM in battery

backup mode, but certain operational details need to be

clear before utilizing the different modes. The most

significant detail is that once V

goes below V

RESET

, then

C communications cease regardless of whether the device

is programmed for I

C operation in battery backup mode.

Table 10 describes 4 different modes possible with using the

BSW and SBIB bits, and how they are affect LVR and battery

backup operation.

• Mode A - In this mode, selection bits indicate a low V

switchover combined with I

C operation in battery backup

mode. In actuality the V

will go below V

RESET

before

switching to battery backup, which will disable I

ANYTIME the device goes into battery backup mode.

Regardless of the battery voltage, the I

C will work down

to the V

RESET

voltage (see Figure 29).

• Mode B - In this mode, the selection bits indicate

switchover to battery backup at V

BAT

, and I

communications in battery backup. In order to

communicate in battery backup mode, the V

RESET

voltage

must be less than the V

BAT

voltage AND V

must be

greater than V

RESET

. Also, pull-ups on the I

C bus pins

must go to V

BAT

to communicate. This mode is the same

as the normal operating mode of the X1228 device.

• Mode C - In this mode, the selection bits indicate a low

switchover combined with no communications in

battery backup. Operation is actually identical to Mode A

with I

C communications down to V

= V

RESET

, then no

communications (see Figure 28).

• Mode D - In this mode, the selection bits indicate

switchover to battery backup at V

< V

BAT

, and no I

communications in battery backup. This mode is unique in

that there is I

C communication as long as V

is higher

than V

RESET

or V

BAT

, whichever is greater. This mode is

the safest for guaranteeing I

C communications only when

there is a Valid V

(see Figure 29).

FIGURE 28. SUPERCAPACITOR CHARGING CIRCUIT

BAT

SUPERCAPACITOR

2.7V TO 5.5V

ISL12027, ISL12027A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

ISL12027AIB27Z-T

Mfr. #:

Buy ISL12027AIB27Z-T

Manufacturer:

Renesas / Intersil

Description:

Real Time Clock REAL TIME CLK/CLNDR W/EEPROM 2 63VSET

Lifecycle:

New from this manufacturer.

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ISL12027AIB27Z-T

ISL12027AIB27Z-T

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