REV. A
AD9847
–10–
Bit Default
Address Content Width Value Register Name Register Description
AFE Registers # Bits 56
00 [5:0] 6 00 oprmode[5:0] AFE Operation Mode (See AFE Register Breakdown)
01 [1:0] 2 00 oprmode[7:6]
02 [5:0] 6 16 ccdgain[5:0] VGA Gain
03 [3:0] 4 02 ccdgain[9:6]
04 [5:0] 6 00 refblack[5:0] Black Clamp Level
05 [1:0] 2 02 refblack[7:6]
06 [5:0] 6 00 ctlmode Control Mode (See AFE Register Breakdown)
07 [5:0] 6 00 pxga gain0 PxGA Color 0 Gain
08 [5:0] 6 00 pxga gain1 PxGA Color 1 Gain
09 [5:0] 6 00 pxga gain2 PxGA Color 2 Gain
0A [5:0] 6 00 pxga gain3 PxGA Color 3 Gain
Miscellaneous/Extra # Bits 26
0F [5:0] 6 00 INITIAL2 See Recommended Power Up Sequence Section. Should be
set to “4” decimal (000100).
16 [0] 1 00 out_cont Output Control (0 = Make All Outputs DC Inactive)
17 [5:0] 6 00 update[5:0] Serial Data Update Control (Sets the line within the field
18 [5:0] 6 00 update[11:6] for serial data update to occur)
19 [0] 1 00 preventupdate Prevent the Update of the VD/HD Updated Registers
1B [5:0] 6 00 doutphase DOUT Phase Control
1C [0] 1 00 disablerestore Disable CCDIN DC Restore Circuit During PBLK
(1 = Disable)
1D [0] 1 00 vdhdpol VD/HD Active Polarity (0 = Low Active, 1 = High Active)
1E [0] 1 01 fieldval Internal Field Pulse Value (0 = Next Field Odd,
1 = Next Field Even)
1F [0] 1 00 hblkretime Re-Sync hblk to h1 Clock
20 [5:0] 6 00 INITIAL1 See Recommended Power Up Sequence. Should be set to
“53” decimal (110101).
26 [0] 1 00 tgcore_rstb TG Core Reset_Bar (0 = Hold TG Core in Reset,
1 = Resume Normal Operation)
Accessing a Double-Wide Register
There are many double-wide registers in the AD9847, e.g.,
oprmode, clpdmtog1_0, and clpdmscp3, and so on. These regis-
ters are configured into two consecutive 6-bit registers with the
least significant six bits located in the lower of the two addresses
and the remaining most significant bits located in the higher of
the two addresses. For example, the six LSBs of the clpdmscp3
register, clpdmscp3[5:0], are located at address 0x81. The most
significant six bits of the clpdmscp3 register, clpdmscp3[11:6],
are located at Address 0x82. The following rules must be fol-
lowed when accessing double-wide registers:
1. When accessing a double-wide register, BOTH addresses
must be written to.
2. The lower of the two consecutive addresses for the double-
wide register must be written to first. In the example of the
clpdmscp3 register, the contents of Address 0x81 must be
written first, followed by the contents of Address 0x82. The
register will be updated after the completion of the write to
Register 0x82, either at the next SL rising edge or the next
VD/HD falling edge.
3. A single write to the lower of the two consecutive addresses
of a double-wide register that is not followed by a write to the
higher address of the registers is not permitted. This will not
update the register.
4. A single write to the higher of the two consecutive addresses of a
double-wide register that is not preceded by a write to the lower
of the two addresses is not permitted. Although the write to the
higher address will update the full double-wide register, the
lower six bits of the register will be written with an indetermi-
nate value if the lower address was not written to first.
