REV. A
–3–
AD9847
ANALOG SPECIFICATIONS
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V,
f
CLI
= 40 MHz, unless otherwise noted.)
Parameter Min Typ Max Unit Notes
CDS
Gain 0 dB
Allowable CCD Reset Transient* 500 mV
Max Input Range before Saturation* 1.0 V p-p
Max CCD Black Pixel Amplitude* 150 mV
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range 1.0 V p-p
Max Output Range 1.6 V p-p
Gain Control Resolution 64 Steps
Gain Monotonicity Guaranteed
Gain Range
Min Gain (32) –2 dB
Med Gain (0) 4 dB
Med Gain (4 dB) Is Default Setting
Max Gain (31) 10 dB
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range 1.6 V p-p
Max Output Range 2.0 V p-p
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range
Low Gain (91) 2 dB
Max Gain (1023) 36 dB
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC Output
Min Clamp Level (0) 0 LSB
Max Clamp Level (255) 63.75 LSB
A/D CONVERTER
Resolution 10 Bits
Differential Nonlinearity (DNL) ± 0.4 ± 1.0 LSB
No Missing Codes Guaranteed
Full-Scale Input Voltage 2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (VRT) 2.0 V
Reference Bottom Voltage (VRB) 1.0 V
SYSTEM PERFORMANCE Specifications Include Entire
Signal Chain
Gain Accuracy Gain Includes 4 dB Default PxGA
Low Gain (91) 5 6 7 dB
Max Gain (1023) 38 dB
Peak Nonlinearity, 500 mV Input Signal 0.2 % 12 dB Gain Applied
Total Output Noise 0.25 LSB rms AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR) 40 dB Measured with Step Change on Supply
*Input signal characteristics defined as follows:
500mV TYP
RESET
TRANSIENT
150mV MAX
OPTICAL
BLACK PIXEL
1V MAX
INPUT
SIGNAL RANGE
Specifications subject to change without notice.
REV. A
AD9847
–4–
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
MASTER CLOCK (CLI)
CLI Clock Period t
CLI
25 ns
CLI High/Low Pulsewidth t
ADC
12.5 ns
Delay from CLI to Internal Pixel
Period Position t
CLIDLY
6ns
EXTERNAL MODE CLAMPING
CLPDM Pulsewidth t
CDM
410Pixels
CLPOB Pulsewidth* t
COB
220 Pixels
SAMPLE CLOCKS
SHP Rising Edge to SHD Rising Edge t
S1
10 ns
DATA OUTPUTS
Output Delay from Programmed Edge t
OD
6ns
Pipeline Delay 9 Cycles
SERIAL INTERFACE
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Falling Edge to SDATA Valid Hold t
DH
10 ns
SCK Falling Edge to SDATA Valid Read t
DV
10 ns
*Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
(C
L
to 29
pF, f
CLI
= 40 MHz, Serial Timing in Figures 3a and 3b,
unless otherwise noted.)
REV. A
AD9847
–5–
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD9847AKST –20°C to +85°CThin Plastic Quad Flatpack (LQFP) ST-48
ABSOLUTE MAXIMUM RATINGS
AVDD1, 2, 3 to AVSS . . . . . . . . . . . . . . . . . . . –0.3 to +3.9 V
DVDD1, 2 to DVSS . . . . . . . . . . . . . . . . . . . . –0.3 to +5.5 V
DVDD3, 4 to DVSS . . . . . . . . . . . . . . . . . . . . –0.3 to +3.9 V
Digital Outputs to DVSS3 . . . . . . . . –0.3 to DVDD3 + 0.3 V
CLPOB, CLPDM, BLK to DVSS4 . –0.3 to DVDD4 + 0.3 V
CLI to AVSS . . . . . . . . . . . . . . . . . . . –0.3 to AVDD + 0.3 V
SCK, SL, SDATA to DVSS4 . . . . . –0.3 to DVDD4 + 0.3 V
VRT, VRB to AVSS . . . . . . . . . . . . . –0.3 to AVDD + 0.3 V
BYP1–3, CCDIN to AVSS . . . . . . . . –0.3 to AVDD + 0.3 V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (10 sec) . . . . . . . . . . . . . . . . . . . . . . 300°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9847 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package . . . . . . . . . . . . . . . . . . .
JA
= 92°C/W

AD9847AKSTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 10-Bit 40 MSPS CCD Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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