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AD9847AKSTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
REV. A
AD9847
–12–
Bit Default
Address Content Width Value Register Name Register Description
CLPOB # Bits 146
84 [0] 1 01 clpobdir CLPOB Internal/External (0 = Internal, 1 = External)
85 [0] 1 00 clpobpol CLPOB External Active Polarity (0 = Low Active, 1 = High Active)
86 [0] 1 01 clpobpol0 Sequence #0: Start Polarity for CLPOB
87 [5:0] 6 0E clpobtog1_0[5:0] Sequence #0: Toggle Position 1 for CLPOB
88 [5:0] 6 00 clpobtog1_0[11:6]
89 [5:0] 6 2B clpobtog2_0[5:0] Sequence #0: Toggle Position 2 for CLPOB
8A [5:0] 6 00 clpobtog2_0[11:6]
8B [0] 1 01 clpobpol1 Sequence #1: Start Polarity for CLPOB
8C [5:0] 6 2B clpobtog1_1[5:0] Sequence #1: Toggle Position 1 for CLPOB
8D [5:0] 6 06 clpobtog1_1[11:6]
8E [5:0] 6 3F clpobtog2_1[5:0] Sequence #1: Toggle Position 2 for CLPOB
8F [5:0] 6 3F clpobtog2_1[11:6]
90 [0] 1 00 clpobspol2 Sequence #2: Start Polarity for CLPOB
91 [5:0] 6 3F clpobtog1_2[5:0] Sequence #2: Toggle Position 1 for CLPOB
92 [5:0] 6 3F clpobtog1_2[11:6]
93 [5:0] 6 3F clpobtog2_2[5:0] Sequence #2: Toggle Position 2 for CLPOB
94 [5:0] 6 3F clpobtog2_2[11:6]
95 [0] 1 01 clpobspol3 Sequence #3: Start Polarity for CLPOB
96 [5:0] 6 3F clpobtog1_3[5:0] Sequence #3: Toggle Position 1 for CLPOB
97 [5:0] 6 3F clpobtog1_3[11:6]
98 [5:0] 6 3F clpobtog2_3[5:0] Sequence #3: Toggle Position 2 for CLPOB
99 [5:0] 6 3F clpobtog2_3[11:6]
000clpobscp0 CLPOB Sequence-Change-Position #0 (Hardcoded to 0)
9A [1:0] 2 03 clpobsptr0 CLPOB Sequence Pointer for SCP #0
9B [5:0] 6 01 clpobscp1[5:0] CLPOB Sequence-Change-Position #1
9C [5:0] 6 00 clpobscp1[11:6]
9D [1:0] 2 01 clpobsptr1 CLPOB Sequence Pointer for SCP #1
9E [5:0] 6 02 clpobscp2[5:0] CLPOB Sequence-Change-Position #2
9F [5:0] 6 00 clpobscp2[11:6]
A0 [1:0] 2 00 clpobsptr2 CLPOB Sequence Pointer for SCP #2
A1 [5:0] 6 37 clpobscp3[5:0] CLPOB Sequence-Change-Position #3
A2 [5:0] 6 03 clpobscp3[11:6]
A3 [1:0] 2 03 clpobsptr3 CLPOB Sequence Pointer for SCP #3
REV. A
AD9847
–13–
Bit Default
Address Content Width Value Register Name Register Description
HBLK # Bits 147
A4 [0] 1 01 hblkdir HBLK Internal/External (0 = Internal, 1 = External)
A5 [0] 1 00 hblkpol HBLK External Active Polarity (0 = Low Active, 1 = High Active)
A6 [0] 1 01 hblkextmask HBLK External Masking Polarity (0 = Mask H1 and H3 Low,
1 = Mask H1 and H3 High)
A7 [0] 1 01 hblkmask0 Sequence #0: Masking Polarity for HBLK
A8 [5:0] 6 3E hblktog1_0[5:0] Sequence #0: Toggle Low Position for HBLK
A9 [5:0] 6 00 hblktog1_0[11:6]
AA [5:0] 6 0D hblkbtog2_0[5:0] Sequence #0: Toggle High Position for HBLK
AB [5:0] 6 06 hblkbtog2_0[11:6]
AC [0] 1 01 hblkmask1 Sequence #1: Masking Polarity for HBLK
AD [5:0] 6 38 hblktog1_1[5:0] Sequence #1: Toggle Low Position for HBLK
AE [5:0] 6 00 hblktog1_1[11:6]
AF [5:0] 6 3C hblktog2_1[5:0] Sequence #1: Toggle High Position for HBLK
B0 [5:0] 6 02 hblktog2_1[11:6]
B1 [0] 1 00 hblkmask2 Sequence #2: Masking Polarity for HBLK
B2 [5:0] 6 3F hblktog1_2[5:0] Sequence #2: Toggle Low Position for HBLK
B3 [5:0] 6 3F hblktog1_2[11:6]
B4 [5:0] 6 3F hblktog2_2[5:0] Sequence #2: Toggle High Position for HBLK
B5 [5:0] 6 3F hblktog2_2[11:6]
B6 [0] 1 01 hblkmask3 Sequence #3: Masking Polarity for HBLK
B7 [5:0] 6 3F hblktog1_3[5:0] Sequence #3: Toggle Low Position for HBLK
B8 [5:0] 6 3F hblktog1_3[11:6]
B9 [5:0] 6 3F hblktog2_3[5:0] Sequence #3: Toggle High Position for HBLK
BA [5:0] 6 3F hblktog2_3[11:6]
000hblkscp0 HBLK Sequence-Change-Position #0 (Hardcoded to 0)
BB [1:0] 2 00 hblksptr0 HBLK Sequence Pointer for SCP #0
BC [5:0] 6 3F hblkscp1[5:0] HBLK Sequence-Change-Position #1
BD [5:0] 6 3F hblkscp1[11:6]
BE [1:0] 2 00 hblksptr1 HBLK Sequence Pointer for SCP #1
BF [5:0] 6 3F hblkscp2[5:0] HBLK Sequence-Change-Position #2
C0 [5:0] 6 3F hblkscp2[11:6]
C1 [1:0] 2 00 hblksptr2 HBLK Sequence Pointer for SCP #2
C2 [5:0] 6 3F hblkscp3[5:0] HBLK Sequence-Change-Position #3
C3 [5:0] 6 3F hblkscp3[11:6]
C4 [1:0] 2 00 hblksptr3 HBLK Sequence Pointer for SCP #3
REV. A
AD9847
–14–
Bit Default
Address Content Width Value Register Name Register Description
PBLK # Bits 146
C5 [0] 1 01 pblkdir PBLK Internal/External (0 = Internal, 1 = External)
C6 [0] 1 00 pblkpol PBLK External Active Polarity (0 = Low Active, 1 = High Active)
C7 [0] 1 01 pblkspol0 Sequence #0: Start Polarity for PBLK
C8 [5:0] 6 3D pblktog1_0[5:0] Sequence #0: Toggle Position 1 for PBLK
C9 [5:0] 6 00 pblktog1_0[11:6]
CA [5:0] 6 2A pblkbtog2_0[5:0] Sequence #0: Toggle Position 2 for PBLK
CB [5:0] 6 06 pblkbtog2_0[11:6]
CC [0] 1 00 pblkspol1 Sequence #1: Start Polarity for PBLK
CD [5:0] 6 2A pblktog1_1[5:0] Sequence #1: Toggle Position 1 for PBLK
CE [5:0] 6 06 pblktog1_1[11:6]
CF [5:0] 6 3F pblktog2_1[5:0] Sequence #1: Toggle Position 2 for PBLK
D0 [5:0] 6 3F pblktog2_1[11:6]
D1 [0] 1 00 pblkspol2 Sequence #2: Start Polarity for PBLK
D2 [5:0] 6 3F pblktog1_2[5:0] Sequence #2: Toggle Position 1 for PBLK
D3 [5:0] 6 3F pblktog1_2[11:6]
D4 [5:0] 6 3F pblktog2_2[5:0] Sequence #2: Toggle Position 2 for PBLK
D5 [5:0] 6 3F pblktog2_2[11:6]
D6 [0] 1 01 pblkspol3 Sequence #3: Start Polarity for PBLK
D7 [5:0] 6 3F pblktog1_3[5:0] Sequence #3: Toggle Position 1 for PBLK
D8 [5:0] 6 3F pblktog1_3[11:6]
D9 [5:0] 6 3F pblktog2_3[5:0] Sequence #3: Toggle Position 2 for PBLK
DA [5:0] 6 3F pblktog2_3[11:6]
000pblkscp0 PBLK Sequence-Change-Position #0 (Hardcoded to 0)
DB [1:0] 2 02 pblksptr0 PBLK Sequence Pointer for SCP #0
DC [5:0] 6 01 pblkscp1[5:0] PBLK Sequence-Change-Position #1
DD [5:0] 6 00 pblkscp1[11:6]
DE [1:0] 2 01 pblksptr1 PBLK Sequence Pointer for SCP #1
DF [5:0] 6 02 pblkscp2[5:0] PBLK Sequence-Change-Position #2
E0 [5:0] 6 00 pblkscp2[11:6]
E1 [1:0] 2 00 pblksptr2 PBLK Sequence Pointer for SCP #2
E2 [5:0] 6 37 pblkscp3[5:0] PBLK Sequence-Change-Position #3
E3 [5:0] 6 03 pblkscp3[11:6]
E4 [1:0] 2 02 pblksptr3 PBLK Sequence Pointer for SCP #3
H1–H4, RG, SHP, SHD # Bits 53
E5 [0] 1 00 h1pol H1/H2 Polarity Control (0 = No Inversion, 1 = Inversion)
E6 [5:0] 6 00 h1posloc H1 Positive Edge Location
E7 [5:0] 6 20 h1negloc H1 Negative Edge Location
E8 [2:0] 3 03 h1drv H1 Drive Strength (0 = OFF, 1 = 3.5 mA, 2 = 7 mA,
3 = 10.5 mA, 4 = 14 mA, 5 = 17.5 mA, 6 = 21 mA, 7 = 24.5 mA)
E9 [2:0] 3 03 h2drv H2 Drive Strength
EA [2:0] 3 03 h3drv H3 Drive Strength
EB [2:0] 3 03 h4drv H4 Drive Strength
EC [0] 1 00 rgpol RG Polarity Control (0 = No Inversion, 1 = Inversion)
ED [5:0] 6 00 rgposloc RG Positive Edge Location
EE [5:0] 6 10 rgnegloc RG Negative Edge Location
EF [2:0] 3 02 rgdrv RG Drive Strength (0 = OFF, 1 = 3.5 mA, 2 = 7 mA,
3 = 10.5 mA, 4 = 14 mA, 5 = 17.5 mA, 6 = 21 mA, 7 = 24.5 mA)
F0 [5:0] 6 24 shpposloc SHP (Positive) Edge Sampling Location
F1 [5:0] 6 00 shdposloc SHD (Positive) Edge Sampling Location
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

AD9847AKSTZ

Mfr. #:
Buy AD9847AKSTZ
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 10-Bit 40 MSPS CCD Signal Processor
Lifecycle:
New from this manufacturer.
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