AD9847AKSTZ Datasheet AD9847AKSTZ, AD9847AKSTZRL | P19-P21

REV. A

AD9847

–18–

(3)(2)

(1)

CLPOB

CLPDM

PBLK

. . .

NOTES

PROGRAMMABLE SETTINGS:

(1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)

(2) FIRST TOGGLE POSITION

(3) SECOND TOGGLE POSITION

. . .

CLAMP

Figure 9. Clamp and Preblank Pulse Placement

(2)

(1)

HBLK

. . .

NOTES

PROGRAMMABLE SETTINGS:

(1) FIRST TOGGLE POSITION = START OF BLANKING

(2) SECOND TOGGLE POSITION = END OF BLANKING

. . .

BLANK

Figure 10. Horizontal Blanking (HBLK) Pulse Placement

Table IV. CLPOB, CLPDM, PBLK Individual Sequence Parameters

SPOL 1b High/Low Starting Polarity of Clamp and Blanking Pulses for Sequences 0–3

TOG1 12b 0–4095 Pixel Location First Toggle Position within the Line for Sequences 0–3

TOG2 12b 0–4095 Pixel Location Second Toggle Position within the Line for Sequences 0–3

Table V. HBLK Individual Sequence Parameters

HBLKMASK 1b High/Low Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High)

HBLKTOG1 12b 0–4095 Pixel Location First Toggle Position within the Line for Sequences 0–3

HBLKTOG2 12b 0–4095 Pixel Location Second Toggle Position within the Line for Sequences 0–3

HORIZONTAL CLAMPING AND BLANKING

The AD9847’s horizontal clamping and blanking pulses are fully

programmable to suit a variety of applications. As with the vertical

timing generation, individual sequences are defined for each

signal and are then organized into multiple regions during image

readout. This allows the dark pixel clamping and blanking patterns

to be changed at each stage of the readout, in order to accom-

modate different image transfer timing and high speed line shifts.

Individual CLPOB, CLPDM, and PBLK Sequences

The AFE horizontal timing consists of CLPOB, CLPDM, and

PBLK, as shown in Figure 9. These three signals are indepen-

dently programmed using the registers in Table IV. SPOL is the

start polarity for the signal, and TOG1 and TOG2 are the first

and second toggle positions of the pulse. All three signals are

active low and should be programmed accordingly. Up to four

individual sequences can be created for each signal.

Individual HBLK Sequences

The HBLK programmable timing shown in Figure 10 is similar to

CLPOB, CLPDM, and PBLK. However, there is no start polarity

control. Only the toggle positions are used to designate the start

and the stop positions of the blanking period. Additionally, there

is a polarity control, HBLKMASK, that designates the polarity of

the horizontal clock signals H1–H4 during the blanking period.

Setting HBLKMASK high will set H1 = H3 = low and H2 =

H4 = high during the blanking, as shown in Figure 11. Up to

four individual sequences are available for HBLK.

REV. A

AD9847

–19–

HBLK

. . .

H1/H3

H2/H4

. . .

THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1)

Figure 11. HBLK Masking Control

Horizontal Sequence Control

The AD9847 uses sequence change positions (SCP) and sequence

pointers (SPTR) to organize the individual horizontal sequences.

Up to four SCPs are available to divide the readout into four

separate regions, as shown in Figure 12. The SCP 0 is always

hard-coded to line 0, and SCP1–3 are register programmable.

During each region bounded by the SCP, the SPTR registers

designate which sequence is used by each signal. CLPOB, CLPDM,

PBLK, and HBLK each have a separate set of SCP. For example,

CLPOBSCP1 will define Region 0 for CLPOB, and in that region

any of the four individual CLPOB sequences may be selected

with the CLPOBSPTR registers. The next SCP defines a new

region, and in that region each signal can be assigned to a different

individual sequence. The sequence control registers are summarized

in Table VI.

UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE

PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.

SEQUENCE CHANGE OF POSITION #1

SEQUENCE CHANGE OF POSITION #2

SEQUENCE CHANGE OF POSITION #3

SINGLE FIELD (1 VD INTERVAL)

CLAMP AND PBLK SEQUENCE REGION 0

SEQUENCE CHANGE OF POSITION #0

(V-COUNTER = 0)

CLAMP AND PBLK SEQUENCE REGION 3

CLAMP AND PBLK SEQUENCE REGION 2

CLAMP AND PBLK SEQUENCE REGION 1

Figure 12. Clamp and Blanking Sequence Flexibility

Table VI. Horizontal Sequence Control Parameters for CLPOB, CLPDM, PBLK, and HBLK

SCP1–SCP3 12b 0–4095 Line Number CLAMP/BLANK SCP to Define Horizontal Regions 0–3

SPTR0–SPTR3 2b 0–3 Sequence Number Sequence Pointer for Horizontal Regions 0–3

REV. A

AD9847

–20–

H-Counter Synchronization

The H-Counter reset occurs on the sixth CLI rising edge following

the HD falling edge. The PxGA steering is synchronized with the

reset of the internal H-Counter (see Figure 13).

POWER-UP PROCEDURE

Recommended Power-Up Sequence

When the AD9847 is powered up, the following sequence is

recommended (refer to Figure 14 for each step).

1. Turn on power supplies for AD9847.

2. Apply the master clock input CLI, VD, and HD.

3. The Precision Timing core must be reset by writing a “0” to the

TGCORE_RSTB Register (Address x026) followed by writ-

ing a “l” to the TGCORE_RSTB Register. This will start the

internal timing core operation. Next, initialize the internal

000 1 12111 0 031100

012345678910111214150123

023

H-COUNTER

RESET

NOTES

1. INTERNAL H-COUNTER IS RESET ON THE SIXTH CLI RISING EDGE FOLLOWING THE HD FALLING EDGE.

2. PxGA STEERING IS SYNCHRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).

3. VD FALLING EDGE SHOULD OCCUR ONE CLOCK CYCLE BEFORE HD FALLING EDGE FOR PROPER PxGA LINE SYNCHRONIZATION.

XXXXXXX

PxGA GAIN

CLI

XXXXXXX

H-COUNTER

(PIXEL COUNTER)

3ns MIN

Figure 13. H-Counter Synchronization

VDD

(INPUT)

SERIAL

WRITES

(OUTPUT)

1 H

ODD FIELD EVEN FIELD

DIGITAL

OUTPUTS

CLOCKS ACTIVE WHEN OUT_CONT REGISTER IS

UPDATED AT VD/HD EDGE

H1/H3, RG

H2/H4

PWR

CLI

(INPUT)

(OUTPUT)

***

Figure 14. Recommended Power-Up Sequences

circuitry by first writing “110101” or “53” decimal to the

INITIAL1 Register (Address x020). Finally, write “000100”

or “4” decimal to the INITIAL2 Register (Address x00F).

4. Write a “1” to the PREVENTUPDATE Register (Address x019).

This will prevent the updating of the serial register data.

5. Write to the desired registers to configure high speed timing

and horizontal timing.

6. Write a “1” to the OUT_CONT Register (Address x016).

This will allow the outputs to become active after the next

VD/HD rising edge.

7. Write a “0” to the PREVENTUPDATE Register (Address x019).

This will allow the serial information to be updated at the

next VD/HD falling edge.

8. The next VD/HD falling edge allows register updates to occur,

including OUT_CONT, which enables all clock outputs.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

AD9847AKSTZ

Mfr. #:

Buy AD9847AKSTZ

Manufacturer:

Analog Devices Inc.

Description:

Analog Front End - AFE 10-Bit 40 MSPS CCD Signal Processor

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AD9847AKSTZ

AD9847AKSTZ

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