Data Sheet ADF4360-8
Rev. D | Page 11 of 24
Lock Detect
MUXOUT can be programmed for one type of lock detect. Dig-
ital lock detect is active high. When LDP in the R counter latch
is set to 0, digital lock detect is set high when the phase error on
three consecutive phase detector cycles is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
INPUT SHIFT REGISTER
The digital section of the ADF4360-8 includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs, DB1 and DB0,
are shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test modes latch is used for factory testing and should not be
programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
Data Latch
C2 C1
0 0 Control Latch
0 1 R Counter
1 0 N Counter (B)
1 1 Test Modes Latch
VCO
The VCO core in the ADF4360-8 uses eight overlapping bands,
as shown in Figure 19, to allow a wide frequency range to be
covered without a large VCO sensitivity (K
V
) and resultant poor
phase noise and spurious performance.
The correct band is chosen automatically by the band select logic
at power-up or whenever the N counter latch is updated. It is
important that the correct write sequence be followed at power-
up. This sequence is
1.
R counter latch
2.
Control latch
3.
N counter latch
During band select, which takes five PFD cycles, the VCO V
TUNE
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
0
1.0
0.5
2.5
2.0
1.5
3.5
3.0
80 85 90 10095 105 115110
FREQUENCY (MHz)
V
TUNE
(V)
04763-019
Figure 19. Frequency vs. V
TUNE
, ADF4360-8, L1 and L2 = 270 nH
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8,
and is controlled by the BSC1 bit and the BSC2 bit in the R
counter latch. Where the required PFD frequency exceeds
1 MHz, the divide ratio should be set to allow enough time for
correct band selection.
After band selection, normal PLL action resumes. The value of
K
V
is determined by the value of inductors used (see the Choos-
ing the Correct Inductance Value section). The ADF4360-8
contains linearization circuitry to minimize any variation of the
product of I
CP
and K
V
.
The operating current in the VCO core is programmable in four
steps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by
the PC1 bit and the PC2 bit in the control latch.
