Data Sheet ADF4360-8
Rev. D | Page 15 of 24
Table 8. N Counter Latch
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)
RSVRSVRSVRSVRSVB1B2B3B4B5B6B7B8B9B10B11B12B13 RSV
CONTROL
BITS
RESERVED
13-BIT B COUNTER
DB21DB22DB23
CP GAIN
RESERVED
RESERVED
CPGRSVRSV
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
CP GAIN OPERATION
CHARGE PUMP CURRENT SETTING 1
IS PERMANENTLY USED
00
CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED
10
N = B; P IS PRESCALER VALUE SET IN THE CONTROL LATCH.
B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY
ADJACENT VALUES OF (N F
REF
), AT THE OUTPUT, N
MIN
IS (P
2
–P).
B13 B12 B11 B3 B2 B1 B COUNTER DIVIDE RATIO
.......... 000 0
00 0
00 0
00 0
0 0 NOT ALLOWED
.......... 0 0 1 NOT ALLOWED
.......... 0 1 0 NOT ALLOWED
.......... 1 1 1 3
.......... ... .
.. .
.. .
.. .
.......... . . . .
.......... . . . .
.......... 111 1
11 1
11 1
11 1
0 0 8188
.......... 1 0 1 8189
.......... 1 1 0 8190
.......... 1 1 1 8191
04763-023
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
ADF4360-8 Data Sheet
Rev. D | Page 16 of 24
Table 9. R Counter Latch
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)
R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6
CONTROL
BITS
BAND
SELECT
CLOCK
ANTI-
BACKLASH
PULSE
WIDTH
14-BIT REFERENCE COUNTER
DB21DB22DB23
LOCK
DETECT
PRECISION
TEST
MODE
BIT
RESERVED
RESERVED
BSC2RSVRSV
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
R14 R13 R12 R3 R2 R1 DIVIDE RATIO
.......... 000 0
00 0
00 0
00 0
01 1
.......... 0 1 0 2
.......... 0 1 1 3
.......... 1 0 0 4
.......... ... .
.. .
.. .
.. .
.......... . . . .
.......... . . . .
.......... 111 1
11 1
11 1
11 1
0 0 16380
.......... 1 0 1 16381
.......... 1 1 0 16382
.......... 1 1 1 16383
THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.
04763-024
LDP LOCK DETECT PRECISION
0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
ABP2 ABP1 ANTIBACKLASH PULSE WIDTH
0 0 3.0ns
0 1 1.3ns
1 0 6.0ns
1 1 3.0ns
BSC2 BSC1 BAND SELECT CLOCK DIVIDER
001
012
104
118
Data Sheet ADF4360-8
Rev. D | Page 17 of 24
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-8 after
power-up is
1.
R counter latch
2.
Control latch
3.
N counter latch
Initial Power-Up
Initial power-up refers to programming the device after the
application of voltage to the AV
DD
, DV
DD
, V
VCO,
and CE pins. On
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-8 during initial power-up to settle.
During initial power-up, a write to the control latch powers up
the device, and the bias currents of the VCO begin to settle. If
these currents have not settled to within 10% of their steady-
state value, and if the N counter latch is then programmed, the
VCO may not oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency band,
and the ADF4360-8 may not achieve lock. If the recommended
interval is inserted, and the N counter latch is programmed, the
band select logic can choose the correct frequency band, and
the device locks to the correct frequency.
The duration of this interval is affected by the value of the
capacitor on the C
N
pin (Pin 14). This capacitor is used to
reduce the close-in noise of the ADF4360-8 VCO. The
recommended value of this capacitor is 10 μF. Using this value
requires an interval of ≥15 ms between the latching in of the
control latch bits and latching in of the N counter latch bits. If a
shorter delay is required, the capacitor can be reduced. A slight
phase noise penalty is incurred by this change, which is further
explained in Table 10.
Table 10. C
N
Capacitance vs. Interval and Phase Noise
C
N
Value
Recommended Interval Between
Control Latch and N Counter Latch
Open-Loop Phase Noise at 10 kHz Offset
L1 and L2 = 18.0 nH L1 and L2 = 110.0 nH L1 and L2 = 560.0 nH
10 μF ≥15 ms −100 dBc/Hz −97 dBc/Hz −99 dBc/Hz
440 nF ≥ 600 μs −99 dBc/Hz −96 dBc/Hz −98 dBc/Hz
CLOCK
POWER-UP
DATA
LE
R COUNTER
LATCH DATA
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
04763-033
Figure 21. ADF4360-8 Power-Up Timing

ADF4360-8BCPZRL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Intg Integer-N VCO Out Freq 65-400
Lifecycle:
New from this manufacturer.
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