ADF4360-8 Data Sheet
Rev. D | Page 12 of 24
OUTPUT STAGE
The RF
OUT
A and RF
OUT
B pins of the ADF4360-8 are connected
to the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 20. To allow the user to
optimize the power dissipation vs. the output power require-
ments, the tail current of the differential pair is programmable
via Bits PL1 and PL2 in the control latch. Four current levels
may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These levels give
output power levels of −9 dBm, −6 dBm, −3 dBm, and 0 dBm,
respectively, using the correct shunt inductor to V
DD
and ac
coupling into a 50 Ω load. Alternatively, both outputs can be
combined in a 1 + 1:1 transformer or a 180° microstrip coupler
(see the Output Matching section).
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to V
DD
.
Another feature of the ADF4360-8 is that the supply current
to the RF output stage is shut down until the device achieves lock,
as measured by the digital lock detect circuitry. This is enabled by
the Mute-Till-Lock Detect (MTLD) bit in the control latch.
VCO
RF
OUT
ARF
OUT
B
BUFFER
04763-020
Figure 20. Output Stage ADF4360-8
Data Sheet ADF4360-8
Rev. D | Page 13 of 24
LATCH STRUCTURE
Table 6 shows the three on-chip latches for the ADF4360-8. The two LSBs decide which latch is programmed.
Table 6. Latch Structure
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (0)
PC1PC2CRM1M2PDPCPCPGMTLDPL1PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 M3
CONTROL
BITS
MUXOUT
CONTROL
CURRENT
SETTING 2
CURRENT
SETTING 1
CORE
POWER
LEVEL
OUTPUT
POWER
LEVEL
DB21DB22DB23
POWER-
DOWN 2
RESERVED
RESERVED
RESERVED
RESERVED
POWER-
DOWN 1
COUNTER
RESET
MUTE-TIL-
LD
CP GAIN
CP
THREE-
STATE
PHASE
DETECTOR
POLARITY
PD2RSVRSV
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (1)
R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6
CONTROL
BITS
BAND
SELECT
CLOCK
ANTI-
BACKLASH
PULSE
WIDTH
14-BIT REFERENCE COUNTER
DB21DB22DB23
LOCK
DETECT
PRECISION
TEST
MODE
BIT
RESERVED
RESERVED
BSC2RSVRSV
RSVRSV
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)
RSVRSVRSVRSVRSVB1B2B3B4B5B6B7B8B9B10B11B12B13 RSV
CONTROL
BITS
RESERVED
13-BIT B COUNTER
CONTROL LATCH
N COUNTER LATCH
R COUNTER LATCH
DB21DB22DB23
CP GAIN
CPG
04763-021
ADF4360-8 Data Sheet
Rev. D | Page 14 of 24
Table 7. Control Latch
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (0) C1 (0)
PC1PC2CRM1M2PDPCPCPGMTLDPL1PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 M3
CONTROL
BITS
MUXOUT
CONTROL
CURRENT
SETTING 2
CURRENT
SETTING 1
CORE
POWER
LEVEL
OUTPUT
POWER
LEVEL
DB21DB22DB23
POWER-
DOWN 2
POWER-
DOWN 1
COUNTER
RESET
MUTE-TIL-
LD
RESERVED
RESERVED
CP GAIN
CP
THREE-
STATE
PHASE
DETECTOR
POLARITY
PD2RSVRSV
CR
0
1
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
PC2
0
0
10
CORE POWER LEVEL
2.5mA
5mA
7.5mA
PC1
0
1
11
10mA
CP
0
1
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
PDP
0
1
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
CPG
0
1
CP GAIN
CURRENT SETTING 1
CURRENT SETTING 2
MTLD
0
1
MUTE-TIL-LOCK DETECT
DISABLED
ENABLED
M3 M2 M1
MUXOUT
THREE-STATE OUTPUT000
001
010
011
100
101
110
111
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
NOT USED
NOT USED
DGND
CE PIN PD2 PD1 MODE
0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
1 0 1 ASYNCHRONOUS POWER-DOWN
1 1 1 SYNCHRONOUS POWER-DOWN
CPI6 CPI5 CPI4
I
CP
(mA)
CPI3 CPI2 CPI1 4.7k
0.31
0.62
0.93
1.25
1.56
1.87
2.18
2.50
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PL2 PL1 OUTPUT POWER LEVEL
CURRENT (USING TUNED LOAD)
–9dBm
–6dBm
–3dBm
0dBm
(USING 50 TO V
VCO
)
–19dBm
–15dBm
–12dBm
–9dBm
0
0
1
1
0
1
0
1
3.5mA
5.0mA
7.5mA
11.0mA
04763-022
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.

ADF4360-8BCPZRL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Intg Integer-N VCO Out Freq 65-400
Lifecycle:
New from this manufacturer.
Delivery:
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