AR0238
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16
Wavelength (nm)
350
Quantum Efficiency (%)
450 550 650 750 850 950 1050 1150
0
10
20
30
40
50
60
70
Red
Green (R)
Green (B)
Blue
IR
Figure 11. Quantum Efficiency RGBIR
ELECTRICAL SPECIFICATIONS
Unless otherwise stated, the following specifications
apply under the following conditions: VDD = 1.8 V –
0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX =
2.8 V ± 0.3 V; VDD_SLVS = 0.4 V – 0.1/+0.2; T
A
= 40°C
to +85°C; output load = 10 pF; frequency = 74.25 MHz;
HiSPi off.
TWOWIRE SERIAL REGISTER INTERFACE
The electrical characteristics of the twowire serial
register interface (S
CLK, SDATA) are shown in Figure 12 and
Table 6.
S
DATA
S
CLK
S Sr P S
t
f
t
r
t
f
t
r
t
SU;DAT
t
HD;STA
t
SU;STO
t
SU;STA
t
BUF
t
HD;DAT
t
HIGH
t
LOW
t
HD;STA
NOTE: Read sequence: For an 8bit READ, read waveforms start after WRITE command and register address are
issued.
Figure 12. TwoWire Serial Bus Timing Parameters
AR0238
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17
Table 6. TwoWire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; T
A
= 25°C
Parameter
Symbol
Standard Mode Fast Mode
Unit
Min Max Min Max
SCLK Clock Frequency
fSCL
0 100 0 400 KHz
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
tHD;STA
4.0 0.6
ms
LOW period of the SCLK clock
tLOW
4.7 1.3
ms
HIGH period of the SCLK clock
tHIGH
4.0 0.6
ms
Setup time for a repeated START
condition
tSU;STA
4.7 0.6
ms
Data hold time
tHD;DAT 0
(Note 11)
3.45
(Note 12)
0 (Note 13) 0.9
(Note 12)
ms
Data setup time
tSU;DAT
250
100 (Note 13)
ns
Rise time of both SDATA and SCLK signals
tr
1000
20 + 0.1Cb
(Note 14)
300 ns
Fall time of both SDATA and SCLK signals
tf
300
20 + 0.1Cb
(Note 14)
300 ns
Setup time for STOP condition
tSU;STO
4.0 0.6
ms
Bus free time between a STOP and START condition
tBUF
4.7 1.3
ms
Capacitive load for each bus line Cb 400 400 pF
Serial interface input pin capacitance CIN_SI 3.3 3.3 pF
SDATA max load capacitance CLOAD_SD
30
30
pF
SDATA pullup resistor RSD 1.5 4.7 1.5 4.7
kW
8. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
9. Twowire control is I2Ccompatible.
10.All values referred to VIHmin = 0.9 VDD and VILmax = 0.1 VDD levels. Sensor EXCLK = 27 MHz.
11. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
12.The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
13.A Fastmode I2Cbus device can be used in a Standardmode I2Cbus system, but the requirement tSU;DAT 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW
period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standardmode I2Cbus specification) before the SCLK line is released.
14.Cb = total capacitance of one bus line in pF.
AR0238
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18
I/O TIMING
By default, the AR0238 launches pixel data, FV, and LV
with the falling edge of PIXCLK. The expectation is that the
user captures DOUT[11:0], FV, and LV using the rising edge
of PIXCLK.
See Figure 13 below and Table 7 on page 18 for I/O
timing (AC) characteristics.
EXTCLK
PIXCLK
Data[11:0]
LINE_VALID/
FRAME_VALID
Pxl_0 Pxl_1 Pxl_2 Pxl_n
t
PFL
t
PLL
t
FP
t
RP
t
F
t
R
90% 90% 90% 90%
10% 10% 10% 10%
t
EXTCLK
t
PD
t
PLH
t
PFH
FRAME_VALID Leads LINE_VALID
by 6 PIXCLKs
FRAME_VALID Trails LINE_VALID
by 6 PIXCLKs
Figure 13. I/O Timing Diagram
Table 7. I/O TIMING CHARACTERISTICS
Symbol Definition Condition Min Typ Max Unit
f
EXTCLK1s
Input Clock Frequency 6 48 MHz
t
EXTCLK1
Input Clock Period 20.8 166 ns
t
R
Input Clock Rise Time 3 ns
t
F
Input Clock Fall Time 3 ns
t
RP
Pixclk Rise Time 2 3.5 5 ns
t
FP
Pixclk Fall Time 2 3.5 5 ns
Clock Duty Cycle 45 50 55 %
t
CP
EXTCLK to PIXCLK Propagation Delay Nominal Voltages,
PLL Disabled
10 14 18 ns
f
PIXCLK
PIXCLK Frequency Default, Nominal
Voltages
6 74.25 MHz
t
PD
PIXCLK to Data Valid Default, Nominal
Voltages
0 2.5 5 ns
t
PFH
PIXCLK to FV HIGH Default, Nominal
Voltages
2 3 6 ns
t
PLH
PIXCLK to LV HIGH Default, Nominal
Voltages
2 3 6 ns
t
PFL
PIXCLK to FV LOW Default, Nominal
Voltages
2 2.5 6 ns
t
PLL
PIXCLK to LV LOW Default, Nominal
Voltages
2 2.5 6 ns
C
LOAD
Output Load Capacitance <10 pF
C
IN
Input Pin Capacitance 2.5 pF
NOTE: I/O timing characteristics are measured under the following conditions:
Temperature is 25°C ambient
10 pF load
1.8 V I/O supply voltage

AR0238CSSC12SHRA0-DR1

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Image Sensors 2MP 1/3 CIS SO
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