AR0238
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23
POWER−ON RESET AND STANDBY TIMING
POWER−UP SEQUENCE
The recommended power−up sequence for the AR0238 is
shown in Figure 14. The available power supplies
(VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA,
VAA_PIX) must have the separation specified below.
1. Turn on VDD_PLL power supply.
2. After 100 ms, turn on VAA and VAA_PIX power
supply.
3. 3. After 100 ms, turn on VDD_IO power supply.
4. After 100 ms, turn on VDD power supply.
5. After 100 ms, turn on VDD_SLVS power supply.
6. After the last power supply is stable, enable
EXTCLK.
7. Assert RESET_BAR for at least 1 ms. The parallel
interface will be tri−stated during this time.
8. Wait 150000 EXTCLKs (for internal initialization
into software standby.
9. Configure PLL, output, and image settings to
desired values.
10. Wait 1ms for the PLL to lock.
11. Set streaming mode (R0x301a[2] = 1).
EXTCLK
V
DD
_SLVS (0.4)
V
AA
_PIX
V
AA
(2.8)
V
DD
_IO (1.8/2.8)
V
DD
(1.8)
V
DD
_PLL (2.8)
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
X
Hard
Reset
Internal
Initialization
Software
Standby PLL Lock Streaming
RESET_BAR
Figure 14. Power Up
Table 19. POWER−UP SEQUENCE
Definition Symbol Min Typ Max Unit
VDD_PLL to VAA/VAA_PIX (Note 17)
t0 0 100 –
ms
VAA/VAA_PIX to VDD_IO t1 0 100 –
ms
VDD_IO to VDD t2 0 100 –
ms
VDD to VDD_SLVS t3 0 100 –
ms
Xtal settle time tx –
30
(Note 15)
– ms
Hard Reset t4
1
(Note 16)
– – ms
Internal Initialization t5 150000 – – EXTCLK
s
PLL Lock Time t6 1 – – ms
15.Xtal settling time is component−dependent, usually taking about 10 – 100 ms.
16.Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
17.It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
others. If the case happens that VDD_PLL is powered after other supplies then sensor may have functionality issues and will experience
high current draw on this supply.
