AR0238
www.onsemi.com
4
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower twowire speed.
3. The parallel interface output pads can be left unconnected if the serial output interface is used.
4. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible
to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the AR0237AT demo
headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
6. I/O signals voltage must be configured to match V
DD
_IO voltage to minimize any leakage currents.
Notes:
FLASH
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
V
DD
_PLLV
DD
_IO V
AA
V
AA
_PIX
A
GND
D
GND
V
AA
_PIXV
AA
V
DD
_IO V
DD
S
DATA
S
CLK
EXTCLK
1.5 kW
2
1.5 kW
2
TRIGGER
OE_BAR
RESET_BAR
TEST
To Controller
From
Controller
Master Clock
(648 MHz)
Digital
I/O
Power
1
Digital
Core
Power
1
Analog
Power
1
Analog
Power
1
Analog
Ground
Digital
Ground
S
ADDR
V
DD
_SLVS
HiSPi Power
either 0.4 V
(SLVS) or
1.8 V (HiV
CM
)
1
V
DD
_PLL
PLL
Power
1
SLVS3_P
SLVS3_N
SLVSC_P
SLVSC_N
V
DD
V
DD
_SLVS
SHUTTER
Figure 2. Typical Configuration: Serial FourLane
HiSPi Interface
AR0238
www.onsemi.com
5
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower twowire speed.
3. The serial interface output pads can be left unconnected if the parallel output interface is used.
4. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible
to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the AR0237AT demo
headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
6. I/O signals voltage must be configured to match V
DD
_IO voltage to minimize any leakage currents.
7. The EXTCLK input is limited to 648 MHz.
Notes:
FRAME_VALID
LINE_VALID
PIXCLK
FLASH
V
DD
_IO V
DD
V
AA
V
AA
_PIX
A
GND
D
GND
V
AA
_PIXV
AA
V
DD
_IO V
DD
EXTCLK
S
DATA
S
CLK
1.5 kW
2
1.5 kW
2
TRIGGER
OE_BAR
RESET_BAR
TEST
To Controller
From
Controller
Master Clock
(648 MHz)
Digital
I/O
Power
1
Digital
Core
Power
1
Analog
Power
1
Analog
Power
1
Analog
Ground
Digital
Ground
D
OUT
[11:0]
S
ADDR
PLL
Power
1
V
DD
_PLL
V
DD
_PLL
SHUTTER
Figure 3. Typical Configuration: Parallel Pixel Data Interface
AR0238
www.onsemi.com
6
6
7
8
9
10
11
12
13
14
15
16
17
18
444546474812345
42
41
40
39
38
37
36
35
34
33
32
31
19 3029282726252423222120
SLVSC_N
SLVS1_P
SLVS1_N
SLVS0_P
SLVS0_N
VDD_SLVS
VDD
SLVS3_P
SLVS3_N
SLVS2_P
SLVS2_N
SLVSC_P
DGND
VDD_PLL
EXTCLK
VAA
AGND
VDD_IO
VDD
DGND
Reserved
VAA
AGND
DGND
SADDR
SDATA
TEST
FLASH
VDD_IO
VDD
VDD_IO
SHUTTER
TRIGGER
OE_BAR
RESET_BAR
SCLK
VDD_IO
VDD
DGND
AGND
VAA_PIX
VAA
ATEST
VAA
VAA_PIX
AGND
DGND
VDD
(Top View Lead Down)
Figure 4. HiSPi 48Lead mPLCC Package
43

AR0238CSSC12SHRA0-DR1

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Image Sensors 2MP 1/3 CIS SO
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union