AR0238
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Table 3. PIN DESCRIPTIONS, HiSPi 48−Lead mPLCC
DS Name mPLCC Pin Type Description
SLVSC_N 1 Output HiSPi serial DDR clock differential N
SLVS1_P 2 Output HiSPi serial data, lane 1, differential P
SLVS1_N 3 Output HiSPi serial data, lane 1, differential N
SLVS0_P 4 Output HiSPi serial data, lane 0, differential P
SLVS0_N 5 Output HiSPi serial data, lane 0, differential N
VDD_SLVS 6 Power 0.3 V−0.6 V or 1.7 V − 1.9 V port to HiSPi Output Driver. Set the High_VCM
(R0x306E[9]) bit to 1 when configuring VDD_SLVS to 1.7 V – 1.9 V.
DGND 7, 14, 18, 32, 40 Power Digital ground
VDD_PLL 8 Power PLL power, 2.8 V nominal
EXTCLK 9 Input External input clock
VAA 10, 16, 35, 37 Power Analog power, 2.8 V nominal
AGND 11, 17, 33, 39 Power Analog ground.
VDD_IO 12, 20, 30, 42 Power I/O supply power, 1.8/2.8 V nominal
VDD 13, 19, 31, 41, 43 Power Digital power, 1.8 V nominal
Reserved 15 − Reserved, NC
FLASH 21 Output Flash control output
TEST 22 Input Manufacturing test enable pin (connect to Dgnd)
SDATA 23 I/O Two−Wire Serial data I/O
SADDR 24 Input Two−Wire Serial address select. 0: 0x20. 1: 0x30
SCLK 25 Input Two−Wire Serial clock input
RESET_BAR 26 Input Asynchronous reset (active LOW). All settings are restored to factory default.
OE_BAR 27 Input Output enable (active LOW)
TRIGGER 28 Input Exposure synchronization input
SHUTTER 29 Output Control for external mechanical shutter. Can be left floating if not used.
VAA_PIX 34, 38 Power Pixel power, 2.8 V nominal
ATEST 36 − Reserved, NC
SLVS3_P 44 Output HiSPi serial data, lane 3, differential P
SLVS3_N 45 Output HiSPi serial data, lane 3, differential N
SLVS2_P 46 Output HiSPi serial data, lane 2, differential P
SLVS2_N 47 Output HiSPi serial data, lane 2, differential N
SLVSC_P 48 Output HiSPi serial DDR clock differential P
NOTE: The 36 thermal connection pads should be all soldered to DGND plane for better thermal conductivity. Refer to PACKAGE
DIMENSIONS for details..
