Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. H1
02/10/2017
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS61WV25616ALL/ALS
IS61WV25616BLL/BLS
IS64WV25616BLL/BLS
FEATURES
HIGH SPEED: (IS61/64WV25616ALL/BLL)
• High-speedaccesstime:8,10,20ns
• LowActivePower:85mW(typical)
• LowStandbyPower:7mW(typical)
CMOS standby
LOW POWER: (IS61/64WV25616ALS/BLS)
• High-speedaccesstime:25,35,45ns
• LowActivePower:35mW(typical)
• LowStandbyPower:0.6mW(typical)
CMOS standby
• Singlepowersupply
— Vdd 1.65V to 2.2V (IS61WV25616Axx)
— Vdd2.4Vto3.6V(IS61/64WV25616Bxx)
• Fullystaticoperation:noclockorrefreshrequired
• Threestateoutputs
• Datacontrolforupperandlowerbytes
• IndustrialandAutomotivetemperaturesupport
• Lead-freeavailable
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM
DESCRIPTION
TheISSI IS61WV25616Axx/Bxx and IS64WV25616Bxx
arehigh-speed,4,194,304-bitstaticRAMsorganizedas
262,144 words by 16 bits. It is fabricated using ISSI's high-
performanceCMOStechnology.Thishighlyreliableprocess
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE.TheactiveLOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61WV25616Axx/Bxx and IS64WV25616Bxx are
packaged in the JEDEC standard 44-pin 400mil SOJ,
44-pinTSOPTypeIIand48-pinMiniBGA(6mmx8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
CE
OE
WE
256K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
FEBRUARY 2017
