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IS61WV25616BLL-10KLI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
Integrated Silicon Solution, Inc. — www.issi.com 13
Rev. H1
02/10/2017
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-20 ns -25 ns -35 ns -45ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
twc WriteCycleTime 20 — 25 — 35 — 45 — ns
tsce CEtoWriteEnd 12 — 18 — 25 — 35 — ns
tAw AddressSetupTime 12 — 15 — 25 — 35 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tsA AddressSetupTime 0 — 0 — 0 — 0 — ns
tPwb LB, UBValidtoEndofWrite 12 — 18 — 30 — 35 — ns
tPwe1 WE Pulse Width (OE=HIGH) 12 — 18 — 30 — 35 — ns
tPwe2 WE Pulse Width (OE=LOW) 17 — 20 — 30 — 35 — ns
tsd Data Setup to Write End 9 — 12 — 15 — 20 — ns
tHd Data Hold from Write End 0 — 0 — 0 — 0 — ns
tHzwe
(3)
WE LOW to High-Z Output — 9 — 12 — 20 — 20 ns
tLzwe
(3)
WEHIGHtoLow-ZOutput 3 — 5 — 5 — 5 — ns
Notes:
1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to V
dd-
0.3VandoutputloadingspeciedinFigure1a.
2. TestedwiththeloadinFigure1b.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdenedbytheoverlapofCE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtothe
rising or falling edge of the signal that terminates the write.
14 Integrated Silicon Solution, Inc. — www.issi.com
Rev. H1
02/10/2017
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
WRITE CYCLE NO. 2
(WE Controlled. OE is HIGH During Write Cycle)
(1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR2.eps
Notes:
1. WRITEisaninternallygeneratedsignalassertedduringanoverlapoftheLOWstatesontheCE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE=(CE)
[ (LB) = (UB) ] (WE).
AC WAVEFORMS
WRITE CYCLE NO. 1
(CE Controlled, OE is HIGH or LOW)
(1 )
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR1.eps
Integrated Silicon Solution, Inc. — www.issi.com 15
Rev. H1
02/10/2017
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 3
(WE Controlled. OE is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATAIN VALID
t
LZWE
t
SD
UB_CEWR3.eps
WRITE CYCLE NO. 4
(LB, UB Controlled, Back-to-Back Write)
(1,3)
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATAIN
VALID
t
LZWE
t
SD
t
PBW
DATAIN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
Notes:
1. TheinternalWritetimeisdenedbytheoverlapofCE = Low, UB and/or LB = Low, and WE = LOW. All signals must be in
validstatestoinitiateaWrite,butanycanbedeassertedtoterminatetheWrite.The
t sA, t HA, t sd, and t Hd timing is referenced
to the rising or falling edge of the signal that terminates the Write.
2. TestedwithOE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

IS61WV25616BLL-10KLI

Mfr. #:
Buy IS61WV25616BLL-10KLI
Manufacturer:
ISSI
Description:
SRAM 4Mb, 2.4v-3.6v, 10ns 256K x 16 Async SRAM
Lifecycle:
New from this manufacturer.
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