REV. B
AD7722
–9–
PIN CONFIGURATION
44-Lead MQFP (S-44B)
3
4
5
6
7
1
2
10
11
8
9
40 39 3841
42
4344 36 35 3437
29
30
31
32
33
27
28
25
26
23
24
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
12
13
14 15 16 17 18 19
20
21 22
AD7722
DGND/DB13
DGND/DB14
DGND/DB15
SYNC
CS
DGND
CAL
AGND
AGND
REF2
AV
DD
DGND/DB2
DGND/DB1
DGND/DB0
CFMT/DRDY
DVAL/RD
DGND
UNI
P/S
AGND
AGND1
CLKIN
TSI/DB3
DOE/DB4
SFMT/DB5
FSI/DB6
SCO/DB7
DV
DD
SDO/DB8
FSO/DB9
DGND/DB10
DGND/DB11
DGND/DB12
XTAL
AGND
AV
DD1
AGND
V
IN
(–)
RESET
V
IN
(+)
AGND
AV
DD
AGND
REF1
PARALLEL MODE PIN FUNCTION DESCRIPTIONS
Mnemonic Pin No. Description
DVAL/RD 5 Read input is a level sensitive logic input. The RD logic level is sensed on the rising edge of CLKIN. This
digital input can be used in conjunction with CS to read data from the device. The output data bus is
enabled when the rising edge of CLKIN senses a logic low level on RD if CS is also low. When RD is
sensed high, the output data bits DB15DB0 will be high impedance.
CFMT/DRDY 4Data Ready Logic Output. A falling edge indicates a new output word is available to be read from the
output data register. DRDY will return high upon completion of a read operation. If a read operation does
not occur between output updates, DRDY will pulse high for two CLKIN cycles before the next output
update. DRDY also indicates when conversion results are available after a SYNC or RESET sequence
and when completing a self-calibration.
DGND/DB15 31 Data Output Bit (MSB).
DGND/DB14 32 Data Output Bit.
DGND/DB13 33 Data Output Bit.
DGND/DB12 34 Data Output Bit.
DGND/DB11 35 Data Output Bit.
DGND/DB10 36 Data Output Bit.
FSO/DB9 37 Data Output Bit.
SDO/DB8 38 Data Output Bit.
SCO/DB7 40 Data Output Bit.
FSI/DB6 41 Data Output Bit.
SFMT/DB5 42 Data Output Bit.
DOE/DB4 43 Data Output Bit.
TSI/DB3 44 Data Output Bit.
DGND/DB2 1 Data Output Bit.
DGND/DB1 2 Data Output Bit.
DGND/DB0 3 Data Output Bit (LSB).
REV. B–10–
AD7722
SERIAL MODE PIN FUNCTION DESCRIPTIONS
Mnemonic Pin No. Description
DVAL/RD 5Data Valid Logic Output. A logic high on DVAL indicates that the conversion result in the output
data register is an accurate digital representation of the analog voltage at the input to the - modu-
lator. The DVAL pin is set low for 8,192 CLKIN cycles if the analog input is overranged and after
initiating CAL, SYNC, or RESET.
CFMT/DRDY 4 Serial Clock Format Logic Input. The clock format pin selects whether the serial data, SDO, is valid
on the rising or falling edge of the serial clock, SCO. When CFMT is logic low, SDO is valid on the
falling edge of SCO if SFMT is low; SDO is valid on the rising edge of SCO if SFMT is high. When
CFMT is logic high, SDO is valid on the rising edge of SCO if SFMT is low; SDO is valid on the
falling edge of SCO if SFMT is high.
TSI/DB3 44 Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set
logic high, DOE will enable the SDO output buffer when it is a logic high, and vice versa. TSI is used
when two AD7722s are connected to the same serial data bus. When using a single ADC, connect
TSI to DGND.
DOE/DB4 43 Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of the SDO
pin. The active state of DOE is determined by the logic level on the TSI pin. When the DOE logic
level equals the level on the TSI pin, the serial data output, SDO, is active. Otherwise, SDO will be
high impedance. SDO can be three-state after a serial data transmission by connecting DOE to FSO.
This input is useful when two AD7722s are connected to the same serial data bus. When using a
single ADC, to ensure SDO is active, connect DOE to DGND so that it equals the logic level of TSI.
SFMT/DB5 42 Serial Data Format Logic Input. The logic level on the SFMT pin selects the format of the FSO
signal. A logic low makes the FSO output a pulse one SCO cycle wide occurring every 32 SCO cycles.
With SFMT set to a logic high, the FSO signal is a frame pulse that is active low for the duration of
the 16 data bit transmission.
FSI/DB6 41 Frame Synchronization Logic Input. The FSI input is used to synchronize the AD7722 serial output
data register to an external source. When the falling edge of CLKIN detects a low-to-high transition,
the AD7722 interrupts the current data transmission, reloads the output serial shift register, resets
SCO, and transmits the conversion result. Synchronization starts immediately, and the next 127
conversions are invalid. In serial mode, DVAL remains high. FSI inputs applied synchronous to the
output data rate do not alter the serial data transmission. If FSI is tied to either a logic high or low,
the AD7722 will generate FSO outputs controlled by the logic level on SFMT.
SCO/DB7 40 Serial Data Clock Output. The serial clock output is synchronous to the CLKIN signal and has a
frequency one-half the CLKIN frequency. A data transmission frame is 32 SCO cycles long.
SDO/DB8 38 Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. A serial
data transmission lasts 32 SCO cycles. After the LSB is output, trailing zeros are output for the
remaining 16 SCO cycles.
FSO/DB9 37 Frame Sync Output. This output indicates the beginning of a word transmission on the SDO pin.
Depending on the logic level of the SFMT pin, the FSO signal is either a positive pulse approximately
one SCO period wide or a frame pulse, which is active low for the duration of the 16 data bit trans-
mission (see Figure 4).
DGND/DB0 3 In serial mode, these pins should be tied to DGND.
DGND/DB1 2
DGND/DB2 1
DGND/DB10 36
DGND/DB11 35
DGND/DB12 34
DGND/DB13 33
DGND/DB14 32
DGND/DB15 31
REV. B
AD7722
–11–
TERMINOLOGY
Signal-to-Noise Plus Distortion Ratio (S/(N+D))
S/(N+D) is the measured signal-to-noise plus distortion ratio
at the output of the ADC. The signal is the rms magnitude of
the fundamental. Noise plus distortion is the rms sum of all
nonfundamental signals and harmonics to half the sampling rate
(f
CLKIN
/128), excluding dc. The ADC is evaluated by applying a
low noise, low distortion sine wave signal to the input pins. By
generating a fast Fourier transform (FFT) plot, the S/(N+D) data
can then be obtained from the output spectrum.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the harmonics to the rms
value of the fundamental. THD is defined as
THD = 20 log
SQRT V
2
2
+V
3
2
+V
4
2
+V
5
2
+V
6
2
()
V
1
where V
1
is the rms amplitude of the fundamental, and V
2
, V
3
,
V
4
, V
5
, and V
6
are the rms amplitudes of the second through
sixth harmonics. The THD is also derived from the FFT plot of
the ADC output spectrum.
Spurious-Free Dynamic Range (SFDR)
Defined as the difference in dB between the peak spurious or har-
monic component in the ADC output spectrum (up to f
CLKIN
/128
and excluding dc) and the rms value of the fundamental. Normally,
the value of this specification will be determined by the largest
harmonic in the output spectrum of the FFT. For input signals
whose second harmonics occur in the stop-band region of the
digital filter, a spur in the noise floor limits the SFDR.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are
those for which neither m nor n is equal to zero. For example, the
second order terms include (fa + fb) and (fa fb), while the third
order terms include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb).
Testing is performed using the CCIF standard, where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in
frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamental, expressed in dB.
Pass-Band Ripple
The frequency response variation of the AD7722 in the defined
pass-band frequency range.
Pass-Band Frequency
The frequency up to which the frequency response variation is
within the pass-band ripple specification.
Cutoff Frequency
The frequency below which the AD7722s frequency response
will not have more than 3 dB of attenuation.
Stop-Band Frequency
The frequency above which the AD7722s frequency response
will be within its stop-band attenuation.
Stop-Band Attenuation
The AD7722s frequency response will not have less than 90 dB
of attenuation in the stated frequency band.
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are minus full scale, a point
0.5 LSB below the first code transition (100 . . . 00 to 100 . . .
01 in bipolar mode, 000 . . . 00 to 000 . . . 01 in unipolar mode)
and plus full scale, a point 0.5 LSB above the last code transition
(011 . . . 10 to 011 . . . 11 in bipolar mode, 111 . . . 10 to
111 . . . 11 in unipolar mode). The error is expressed in LSB.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between two adjacent codes in the ADC.
Common-Mode Rejection Ratio
The ability of a device to reject the effect of a voltage applied to
both input terminals simultaneouslyoften through variation of
a ground levelis specified as a common-mode rejection ratio.
CMRR is the ratio of gain for the differential signal to the gain
for the common-mode signal.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
(00 . . . 000 to 00 . . . 001) from the ideal differential voltage
(V
IN
(+) V
IN
() + 0.5 LSB) when operating in the unipolar mode.
Bipolar Offset Error
This is the deviation of the midscale transition code
(111 . . . 11 to 000 . . . 00) from the ideal differential voltage
(V
IN
(+) V
IN
() 0.5 LSB) when operating in the bipolar mode.
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above full scale. The last transition should occur for an analog
value 1 1/2 LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.

AD7722ASZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 16-Bit 195 kSPS
Lifecycle:
New from this manufacturer.
Delivery:
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