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AD7722ASZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
REV. B
AD7722
–3–
A Version
Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS (Excluding CLKIN)
V
INH
, Input High Voltage 2.0 V
V
INL
, Input Low Voltage 0.8 V
CLOCK INPUT (CLKIN)
V
INH
, Input High Voltage 4.0 V
V
INL
, Input Low Voltage 0.4 V
ALL LOGIC INPUTS
I
IN
, Input Current V
IN
= 0 V to DV
DD
±10 µA
C
IN
, Input Capacitance 10 pF
LOGIC OUTPUTS
V
OH
, Output High Voltage |I
OUT
| = 200 µA 4.0 V
V
OL
, Output Low Voltage |I
OUT
| = 1.6 mA 0.4 V
POWER SUPPLIES
AV
DD
, AV
DD1
4.75 5.25 V
DV
DD
4.75 5.25 V
I
DD
Total from AV
DD
and DV
DD
75 mA
Power Consumption 375 mW
NOTES
1
Operating temperature range is –40°C to +85°C (A Version).
2
Measurement Bandwidth = 0.5 × f
S
; Input Level = –0.05 dB.
3
T
A
= 25°C to 85°C/T
A
= T
MIN
to T
MAX
.
4
Applies after calibration at temperature of interest.
5
Gain error excludes reference error. The ADC gain is calibrated w.r.t. the voltage on the REF2 pin.
Specifications subject to change without notice.
REV. B–4–
AD7722
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AV
DD
, AV
DD1
to AGND . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AV
DD
, AV
DD1
to DVDD . . . . . . . . . . . . . . . . . . . –1 V to +1 V
AGND, AGND1 to DGND . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DV
DD
+ 0.3 V
Digital Outputs to DGND . . . . . . . . . –0.3 V to DV
DD
+ 0.3 V
V
IN
(+), V
IN
(–) to AGND . . . . . . . . . . –0.3 V to AV
DD
+ 0.3 V
REF1 to AGND . . . . . . . . . . . . . . . . –0.3 V to AV
DD
+ 0.3 V
REF2 to AGND . . . . . . . . . . . . . . . . –0.3 V to AV
DD
+ 0.3 V
DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Input current to any pin except the supplies
2
. . . . . . . . ±10 mA
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . 72°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . 20°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional opera-
tion of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Transient currents up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Package Package
Model Temperature Description Option
AD7722AS –40°C to +85°C 44-Lead MQFP S-44B
EVAL-AD7722CB Evaluation Board
I
OL
1.6mA
I
OH
200A
1.6V
C
L
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Timing Specifications
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7722 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
AD7722
–5–
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
CLKIN Frequency f
CLK
0.3 12.5 15 MHz
CLKIN Period (t
CLK
= 1/f
CLK
)t
1
0.067 0.08 3.33 µs
CLKIN Low Pulse Width t
2
0.45 × t
1
0.55 × t
1
CLKIN High Pulse Width t
3
0.45 × t
1
0.55 × t
1
CLKIN Rise Time t
4
5ns
CLKIN Fall Time t
5
5ns
FSI Low Time t
6
2t
CLK
FSI Setup Time t
7
20 ns
FSI Hold Time t
8
20 ns
CLKIN to SCO Delay t
9
40 ns
SCO Period
1
t
10
2t
CLK
SCO Transition to FSO High Delay t
11
410 ns
SCO Transition to FSO Low Delay t
12
410 ns
SCO Transition to SDO Valid Delay t
13
38 ns
SCO Transition from FSI
2
t
14
2.5 t
CLK
SDO Enable Delay Time t
15
30 45 ns
SDO Disable Delay Time t
16
10 30 ns
DRDY High Time t
17
2t
CLK
Conversion Time
1
t
18
64 t
CLK
DRDY to CS Setup Time t
19
0ns
CS to RD Setup Time t
20
0ns
RD Pulse Width t
21
t
CLK
+ 20 ns
Data Access Time after RD Falling Edge
3
t
22
t
CLK
+ 40 ns
Bus Relinquish Time after RD Rising Edge t
23
t
CLK
+ 40 ns
CS to RD Hold Time t
24
0ns
RD to DRDY High Time t
25
1t
CLK
SYNC/RESET Input Pulse Width t
26
10 ns
DVAL Low Delay from SYNC/RESET t
27
40 ns
SYNC/RESET Low Time after CLKIN Rising t
28
10 t
CLK
– 10 ns
DRDY High Delay after SYNC/RESET Low t
29
50 ns
DRDY Low Delay after SYNC/RESET Low
1
t
30
(8192 + 64) t
CLK
DVAL High Delay after SYNC/RESET Low
1
t
31
8192 t
CLK
CAL Setup Time t
34
10 ns
CAL Pulse Width t
35
12 t
CLK
Calibration Delay from CAL High t
36
64 t
CLK
Unipolar Input Calibration Time, (UNI = 0)
1, 4
t
37
(3 × 8192 + 2 × 512) t
CLK
Bipolar Input Calibration Time, (UNI = 1)
1, 4
t
37
(4 × 8192 + 3 × 512) t
CLK
Conversion Results Valid, (UNI = 0)
1
t
38
(3 × 8192 + 2 × 512 + 64) t
CLK
Conversion Results Valid, (UNI = 1)
1
t
38
(4 × 8192 + 3 × 512 + 64) t
CLK
NOTES
1
Guaranteed by design.
2
Frame sync is initiated on falling edge of CLKIN.
3
With RD synchronous to CLKIN, t
22
can be reduced up to 1 t
CLK
.
4
See Figure 8.
Specifications subject to change without notice.
(AV
DD
= 5 V ⴞ 5%, DV
DD
= 5 V ⴞ 5%, AGND = DGND = 0 V, C
L
= 50 pF, T
A
= T
MIN
to T
MAX
,
f
CLKIN
= 12.5 MHz, SFMT = Logic Low or High, CFMT = Logic Low or High.)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD7722ASZ

Mfr. #:
Buy AD7722ASZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 16-Bit 195 kSPS
Lifecycle:
New from this manufacturer.
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