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AD7722ASZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
REV. B
AD7722
–15–
APPLYING THE AD7722
Analog Input Range
The AD7722 uses differential inputs to provide common-mode
noise rejection (i.e., the converted result will correspond to the
differential voltage between the two inputs). The absolute voltage
on both inputs must lie between AGND and AV
DD
.
In unipolar mode, the full-scale analog input range
(V
IN
(+) – V
IN
(–)) is 0 V to V
REF2
. The output code is straight
binary in the unipolar mode with 1 LSB = 38 µV. The ideal transfer
function is shown in Figure 11.
In bipolar mode, the full-scale input range is ±V
REF2
/2. The
bipolar mode allows complementary input signals. As another
example, in bipolar mode, V
IN
(–) can be connected to a dc bias
voltage to allow a single-ended input on V
IN
(+) equal to V
BIAS
±V
REF2
/2. In bipolar mode, the output code is twos complement
with 1 LSB = 38 µV. The ideal transfer function is shown in
Figure 12.
111...111
111...110
111...101
111...100
000...011
000...010
000...001
000...000
OUTPUT
CODE
0V
V
REF2
–1LSB
DIFFERENTIAL INPUT VOLTAGE V
IN
(+) – V
IN
(–)
Figure 11. Unipolar Mode Transfer Function
111...111
111...110
100...001
100...000
000...010
000...001
000...000
OUTPUT
CODE
0V
+V
REF2
/2 – 1LSB
DIFFERENTIAL INPUT VOLTAGE V
IN
(+) – V
IN
(–)
–V
REF2
011...111
011...110
Figure 12. Bipolar Mode Transfer Function
Differential Inputs
The analog input to the modulator is a switched capacitor design.
The analog signal is converted into charge by highly linear
sampling capacitors. A simplified equivalent circuit diagram of
the analog input is shown in Figure 13. A signal source driving
the analog input must be able to provide the charge onto the
sampling capacitors every half CLKIN cycle and settle to the
required accuracy within the next half cycle.
18
Φ
A
Φ
B
Φ
A
Φ
B
16
2pF
2pF
AC
GROUND
500
Φ
A
Φ
B
Φ
A
Φ
B
CLKIN
V
IN
(+)
V
IN
(–)
AD7722
500
Figure 13. Analog Input Equivalent Circuit
Since the AD7722 samples the differential voltage across its
analog inputs, low noise performance is attained with an input
circuit that provides low common-mode noise at each input.
The amplifiers used to drive the analog inputs play a critical role
in attaining the high performance available from the AD7722.
When a capacitive load is switched onto the output of an op amp,
the amplitude will momentarily drop. The op amp will try to
correct the situation and, in the process, will hit its slew rate limit.
This nonlinear response, which can cause excessive ringing, can
lead to distortion. To remedy the situation, a low-pass RC filter
can be connected between the amplifier and the input to the
AD7722 as shown in Figure 14. The external capacitor at each
input aids in supplying the current spikes created during the
sampling process. The resistor in this diagram, as well as creating
the pole for the antialiasing, isolates the op amp from the transient
nature of the load.
ANALOG
INPUT
R
C
AD7722
V
IN
(+)
V
IN
(–)
R
C
Figure 14. Simple RC Antialiasing Circuit
The differential input impedance of the AD7722 switched capacitor
input varies as a function of the CLKIN frequency, given by the
equation
Z
f
k
IN
CLKIN
=
×
10
4
9
Ω
REV. B–16–
AD7722
Even though the voltage on the input sampling capacitors may not
have enough time to settle to the accuracy indicated by the resolu-
tion of the AD7722, as long as the sampling capacitor charging
follows the exponential curve of RC circuits, only the gain
accuracy suffers if the input capacitor is switched away too early.
An alternative circuit configuration for driving the differential
inputs to the AD7722 is shown in Figure 15.
R
100
C
2.7nF
AD7722
V
IN
(+)
V
IN
(–)
C
2.7nF
C
2.7nF
R
100
Figure 15. Differential Input with Antialiasing
A capacitor between the two input pins sources or sinks charge
to allow most of the charge that is needed by one input to be
effectively supplied by the other input. This minimizes undesir-
able charge transfer from the analog inputs to and from ground.
The series resistor isolates the operational amplifier from the
current spikes created during the sampling process and provides
a pole for antialiasing. The –3 dB cutoff frequency (f
3 dB
) of the
antialias filter is given by Equation 1, and the attenuation of the
filter is given by Equation 2.
f
RC
dB3
1
6
=
(1)
Attenuation log
f
f
dB
=+
20 1 / 1
3
2
(2)
The choice of the filter cutoff frequency will depend on the
amount of roll-off that is acceptable in the pass band of the
digital filter and the required attenuation at the first image
frequency. For example, when operating the AD7722 with a
12.5 MHz clock, with the typical values of R and C of 100 Ω and
2.7 nF shown in Figure 15, the –3 dB cutoff frequency (f
3 dB
)
creates less than 1 dB of in-band (90.625 kHz) roll-off and
provides about 36 dB attenuation at the first image frequency.
The capacitors used for the input antialiasing circuit must have
low dielectric absorption to avoid distortion. Film capacitors such
as polypropylene, polystyrene, or polycarbonate are suitable. If
ceramic capacitors are used, they must have NP0 dielectric.
Applying the Reference
The reference circuitry used in the AD7722 includes an on-chip
2.5 V band gap reference and a reference buffer circuit. The block
diagram of the reference circuit is shown in Figure 16. The inter-
nal reference voltage is connected to REF1 through a 3 kΩ resistor
and is internally buffered to drive the analog modulator’s switched
cap DAC (REF2). When using the internal reference, connect
100 nF between REF1 and AGND. If the internal reference is
required to bias external circuits, use an external precision op
amp to buffer REF1.
24
3k
AD7722
REFERENCE
BUFFER
22
1V
2.5V
REFERENCE
SWITCHED-CAP
DAC REF
REF1
REF2
COMPARATOR
100nF
Figure 16. Reference Circuit Block Diagram
The AD7722 can operate with its internal reference, or an
external reference can be applied in two ways. An external
reference can be connected to REF1, overdriving the internal
reference. However, there will be an error introduced due to the
offset of the internal buffer amplifier. For the lowest system gain
errors when using an external reference, REF1 is grounded
(disabling the internal buffer) and the external reference is
connected to REF2.
In all cases, since the REF2 voltage connects to the analog
modulator, a 100 nF capacitor must connect directly from
REF2 to AGND. The external capacitor provides the charge
required for the dynamic load presented at the REF2 pin
(Figure 17).
Φ
A
Φ
B
Φ
B
24
4pF
Φ
A
Φ
B
Φ
A
Φ
B
CLKIN
REF2
AD7722
Φ
A
4pF
SWITCHED-CAP
DAC REF
100nF
Figure 17. REF2 Equivalent Input Circuit
The AD780 is ideal to use as an external reference with the
AD7722. Figure 18 shows a suggested connection diagram.
AD780
1
2
3
4
8
7
6
5
NC
+V
IN
TEMP
GND
O/P
SELECT
NC
V
OUT
TRIM
22nF
1F
24
REF2
AD7722
22F
100nF
22
REF1
5V
Figure 18. External Reference Circuit Connection
REV. B
AD7722
–17–
Input Circuits
Figures 19 and 20 show two simple circuits for bipolar mode
operation. Both circuits accept a single-ended bipolar signal
source and create the necessary differential signals at the input
to the ADC.
The circuit in Figure 19 creates a 0 V to 2.5 V signal at the
V
IN
(+) pin to form a differential signal around an initial bias of
1.25 V. For single-ended applications, best THD performance
is obtained with V
IN
(–) set to 1.25 V rather than 2.5 V. The
input to the AD7722 can also be driven differentially with a
complementary input, as shown in Figure 20.
In this case, the input common-mode voltage is set to 2.5 V.
The 2.5 V p-p full-scale differential input is obtained with a
1.25 V p-p signal at each input in antiphase. This configuration
minimizes the required output swing from the amplifier circuit
and is useful for single-supply applications.
12pF
1k 1k
1k
12pF
1k
100nF
374k
1nF
V
IN
(–)
1/2
OP275
V
IN
(+)
18
REF1
22
REF2
100nF
24
AD7722
DIFFERENTIAL
INPUT = 2.5V p-p
V
IN
(–) BIAS
VOLTAGE = 1.25V
AIN =
1.25V
16
1/2
OP275
1k
374k
10nF
1nF
Figure 19. Single-Ended Analog Input Circuit for
Bipolar Mode Operation
12pF
1k
AIN =
0.625V
1k
1k
12pF
1k
1/2
OP275
100nF
R
R
1nF
V
IN
(–)
1nF
1/2
OP275
16
V
IN
(+)
18
DIFFERENTIAL
INPUT = 2.5V p-p
COMMON-MODE
VOLTAGE = 2.5V
REF1
22
OP07
REF2
100nF
24
AD7722
Figure 20. Single-Ended-to-Differential Analog
Input Circuit for Bipolar Mode Operation
The 1 nF capacitors at each ADC input store charge to aid the
amplifier settling as the input is continuously sampled. A resistor
in series with the drive amplifier output and the 1 nF input
capacitor may also be used to create an antialias filter.
Clock Generation
The AD7722 contains an oscillator circuit to allow a crystal or
an external clock signal to generate the master clock for the ADC.
The connection diagram for use with the crystal is shown in
Figure 21. Consult the crystal manufacturer’s recommendation
for the load capacitors.
1M
XTAL CLKIN
AD7722
Figure 21. Crystal Oscillator Connection
An external clock must be free of ringing and have a minimum
rise time of 5 ns. Degradation in performance can result as high
edge rates increase coupling that can generate noise in the
sampling process. The connection diagram for an external clock
source (Figure 22) shows a series damping resistor connected
between the clock output and the clock input to the AD7722.
The optimum resistor will depend on the board layout and the
impedance of the trace connecting to the clock input.
CLOCK
CIRCUITRY
CLKIN
AD7722
25–150
Figure 22. External Clock Oscillator Connection
A low phase noise clock should be used to generate the ADC
sampling clock because sampling clock jitter effectively modulates
the input signal and raises the noise floor. The sampling clock
generator should be isolated from noisy digital circuits, grounded,
and heavily decoupled to the analog ground plane.
The sampling clock generator should be referenced to the analog
ground plane in a split-ground system. However, this is not
always possible because of system constraints. In many cases,
the sampling clock must be derived from a higher frequency
multipurpose system clock that is generated on the digital ground
plane. If the clock signal is passed between its origin on a digital
ground plane to the AD7722 on the analog ground plane, the
ground noise between the two planes adds directly to the clock
and will produce excess jitter. The jitter can cause degradation in the
signal-to-noise ratio and can also produce unwanted harmonics.
This can be remedied somewhat by transmitting the sampling
clock signal as a differential one, using either a small RF trans-
former or a high speed differential driver and receiver, such as
the PECL. In either case, the original master system clock
should be generated from a low phase noise crystal oscillator.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD7722ASZ

Mfr. #:
Buy AD7722ASZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 16-Bit 195 kSPS
Lifecycle:
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